Parallel symbol synchronization system and method for all-digital receiver

Abstract

The invention relates to a parallel symbol synchronization method and system for an all-digital receiver. The method includes: performing serial-to-parallel conversion on input data, and outputting parallel signals in units of fixed-length frames; interpolating the parallel signals through interpolation filters of a parallel pipeline structure according to interpolation parameters and structure indication signals; using Gardner algorithm to obtain average timing An error signal; filtering the average clock error signal to obtain a control signal; updating interpolation parameters and a structure indicating signal according to the control signal; outputting a symbol frame and outputting an indicating signal according to the structure indicating signal. The invention is suitable for high-speed digital receivers whose communication symbol rate is much higher than the main frequency of the receiving system, completes symbol synchronization with a low-speed control flow, and reduces the requirement of the high-speed communication system on the main frequency of the receiver.

Description

technical field [0001] The invention relates to the technical field of digital information transmission, in particular to a parallel all-digital symbol synchronization method and system. Background technique [0002] In a digital communication system, the transmit clock and the receive clock are independent of each other, and the inconsistency of clock frequency and phase inevitably occurs, so symbol synchronization is a key technology in high-speed demodulation systems. [0003] Traditional serial all-digital symbol synchronization schemes such as figure 1 As shown, the sampling signal obtained based on an independent local clock is synchronized with the signal symbol rate through point-by-point adjustment of the interpolator. The specific control process is: the interpolated signal y(k) is output to the clock error detector to extract the timing error signal e; the loop filter filters e to obtain the control signal w; the control signal w is output to the control unit to ...

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Problems solved by technology

[0004] Prior Art [1] CN200910238394.3 "Parallel Interpolation Device and Method for All-Digital Receiver" The main frequency of the control unit is still 1 / T s and the clock period is adjusted by T s It is carried out as a unit, so it does not play a role in reducing the main frequency of the receiver's core processing device

[2] CN200910241629.4 "Parallel non-data-assisted clock recovery method and its system" requires a sufficiently large FIFO to ensure that no data overflow occurs, so it is suitable for burst communication systems, but not suitable for continuous communication systems

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