Formation method of semiconductor structure

Abstract

The present invention provides a forming method of a semiconductor structure. A first dielectric layer and a first hard mask layer located on the first dielectric layer are formed at the surface of the front surface of a wafer in order, then the back surface of the wafer is cleaned by adopting a DSP solution. The back surface of the wafer is cleaned by adopting the DSP solution, the DSP solution can clearly remove the remove residual metal ions on the back surface of the wafer, and in the process for cleaning the back surface by adopting the DSP solution, the etching rate of the DSP solution in the wafer material and the first dielectric layer material is low to prevent the surface of the first dielectric layer at the edge of the front surface of the wafer and the surface of the front surface of the wafer from forming etching defects so that a second dielectric layer and a second hard mask layer on the edge of the wafer cannot be hung in the air when the second dielectric layer and thesecond hard mask layer are formed on the first dielectric layer subsequently to prevent the edges of the second dielectric layer and the second hard mask layer from forming peeling defects.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] Multilayer interconnection technology has become an important part of the manufacturing process of large-scale integrated circuits and ultra-large-scale integrated circuits. The current high-performance VLSI has as many as 7 to 10 layers of metal wiring. [0003] A multilayer interconnection structure usually includes multiple layers of metal wiring, which are interconnected through a plug structure in an insulating material. The process of forming the plug is a process of filling a via hole or a trench with a metal material. [0004] Taking the formation of a layer of interconnection structure as an example for illustration, the formation process includes: Reference figure 1 , providing a wafer 101, which has several active regions (not shown in the figure) on the wafer 101, and semiconduc...

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Problems solved by technology

[0005] The edges of the second dielectric layer 103 and the second hard mask layer 104 are prone to peeling defects in the manufacturing process of the existing interconnect structure.

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