Die encapsulation in oxide bonded wafer stack

Abstract

Structures and methods of fabricating semiconductor wafer assemblies (100) encapsulate at least one die (108, 202, 402) in a cavity (110, 204, 404) etched into an oxide bonded semiconductor wafer stack (102+104, 206+208, 406+408). The methods generally include the steps of positioning the die (108, 202, 402) in the cavity (110, 204, 404), mechanically and electrically mounting the die (108, 202, 402) to the wafer stack (102+104, 206+208, 406+408), and encapsulating the die (108, 202, 402) within the cavity (110, 204, 404) by bonding a lid wafer (106, 210, 410) to the wafer stack (102+104, 206+208, 406+408) in one of multiple ways. Semiconductor processing steps are applied to construct the assemblies (e.g., deposition, annealing, chemical and mechanical polishing, etching, etc.) and connecting the die (e.g., bump bonding, wire interconnecting, ultrasonic bonding, oxide bonding, etc.) according to the embodiments described above. The cavity (110, 404) may be hermetically sealed to encapsulate the semiconductor die (108, 402). The wafer assembly (100) may be diced to produce one or more semiconductor chips, each semiconductor chip including one or more encapsulated semiconductor die(108, 202, 402). A thermal interface (164, 170, 412) may be comprised between the semiconductor die (108, 402) and one or more of the wafers (102, 104, 106, 406, 408, 410). The wafer stack (102+104, 406+408) and the lid wafer (106, 410) may be oxide bonded together. Alternatively, the wafer stack (206+208) and the lid wafer (210) may be bump (214) bonded so as to define an air gap (224) providingthermal isolation from the cavity (204). One of the wafers (102, 104, 106) may define a conduit (168) to the cavity (110) from the exterior of the wafer assembly (100), wherein the conduit (168) and the cavity (110) are at least partially filled with a thermally conductive material, are evacuated and sealed providing a vacuum package or are evacuated and backfilled with a liquid or gas before sealing.

Description

Background technique [0001] The present disclosure relates to the fabrication of integrated circuits, semiconductor devices, and other miniaturized devices, and more particularly, to the fabrication of three-dimensional integrated circuits (3D-ICs) including semiconductor dies packaged in oxide-bonded wafer stacks. [0002] As semiconductor device sizes have decreased, 3D device integration has become a desirable approach to increasing the density of integrated circuits and / or semiconductor devices, offering much smaller form factors and higher performance and lower power than 2D designs . 3D-IC components include two or more stacked layers of active electronic components (e.g., sensors and readout circuits) that use horizontal intra-layer and vertical (through-silicon vias, TSV) inter-layer connections such that they behave as single device. Package-to-package stacking and die-to-die (D2D) stacking allow selection of "known good dies" for stacking, and can provide higher yi...

AI Technical Summary

Problems solved by technology

Package-to-package stacking and die-to-die (D2D) stacking allow selection of "known good die" for stacking and can provide higher yields but limited performance improvement over 3D

2D methods sometimes use wirebonding that requires long connections, which slows things down and limits the number of possible connections

Known techniques are available for direct metal-to-metal bonding of integrated circuit dies to silicon wafers, but these techniques have limitations in processing stress, yield, interconnect density, and thermal constraints for high-level wafer stacked die

Other technologies have integrated multiple dies onto an interposer, but have neither extended the stack further beyond 2-3 layers in the z-axis, nor achieved heterogeneous or hermetically sealed devices

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