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Memory cell array and method of forming same

A cell array and memory technology, applied in the direction of electrical components, semiconductor devices, electric solid-state devices, etc., can solve problems that affect the overall integrated circuit performance of the operating voltage

Active Publication Date: 2021-04-09
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As integrated circuits have become smaller and more complex, the resistance of the conductive lines within these digital devices has also changed, affecting the operating voltage of these digital devices and the performance of the overall integrated circuit

Method used

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  • Memory cell array and method of forming same
  • Memory cell array and method of forming same
  • Memory cell array and method of forming same

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Embodiment Construction

[0174] The ensuing disclosure provides various implementations or examples to achieve the presented features of the subject matter. Specific embodiments of constituent elements, materials, numerical values, steps, arrangements, etc. are described below to simplify the present disclosure. These are of course only examples and not restrictive. Other constituent elements, materials, values, steps, arrangements, etc. are also contemplated. For example, in the ensuing description, a second feature is formed on or over a first feature, possibly including embodiments in which the first and second features form direct contact, and possibly between the first and second features. Forming additional features is therefore also possible including embodiments where the first and second features are not in direct contact. Additionally, the disclosure may repeat reference numbers and / or letters in various embodiments. Such repetition is for simplicity and clarity and does not imply a relat...

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PUM

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Abstract

A memory cell array and its forming method. The memory cell array includes memory cells in a first column, memory cells in a second column, a first bit line, a second bit line, and a source line. The memory cells of the second column are separated from the memory cells of the first column in the first direction. The memory cells in the first column and the memory cells in the second column are arranged in the second direction. The first bit line is coupled to the memory cells of the first vertical row and extends along the second direction. The second bit line is coupled to the memory cells of the second column and extends along the second direction. The source lines extend along the second direction and are coupled to the memory cells of the first column and the memory cells of the second column.

Description

technical field [0001] This disclosure is about the layout design of memory cell arrays. Background technique [0002] The semiconductor integrated circuit (IC) industry has produced a wide variety of digital devices to address issues in many different fields. Some of these digital devices, such as memory macros, are configured for storage of data. As integrated circuits have become smaller and more complex, the resistance of the conductive lines within these digital devices has also changed, thereby affecting the operating voltage of these digital devices and the performance of the overall integrated circuit. Contents of the invention [0003] An aspect of the present disclosure is a memory cell array, comprising: memory cells in a first column, memory cells in a second column, a first bit line, a second bit line, and a source line. The memory cells of the second vertical row are separated from the memory cells of the first vertical row in the first direction, and the m...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/24H01L27/02
CPCH01L27/0207H10B63/30H10B63/80G11C2213/79G11C2213/32G11C13/003G11C13/0007G11C2213/82G06F30/392G06F30/394H10B63/84H10B61/22H10N70/826H10N70/8833H10N70/011G06F30/39H10B69/00H10N70/841
Inventor 翁啟翔池育德
Owner TAIWAN SEMICON MFG CO LTD