Logic gate circuit

Abstract

The embodiment of the invention provides a logic gate circuit. The logic gate circuit comprises a pull-up circuit and a pull-down circuit, the pull-up circuit comprises N P-type TFETs which are connected in parallel. The pull-down circuit comprises N N type MOSFETs or FINFETs which are connected in series, wherein N is greater than 1; wherein grid electrodes of the N P-type first field effect transistors are electrically connected with grid electrodes of the N N-type second field effect transistors one by one and serve as N input ends of the logic gate circuit, and drain electrodes of the N P-type first field effect transistors serve as output ends of the logic gate circuit. Because the TFET can normally operate when the power supply voltage is relatively low, the power consumption of thelogic gate circuit is relatively low. Meanwhile, the driving current of the MOSFET or the FINFET is relatively large, so that the problem of relatively long delay of a logic gate circuit is solved. Thus, the problem of relatively long delay is further solved on the premise of ensuring relatively low power consumption.

Description

technical field [0001] The embodiments of the present application relate to the field of electronic circuits, and in particular, to a logic gate circuit. Background technique [0002] A logic gate circuit refers to a circuit that can realize basic logic operations such as "NOR", "NAND", "OR", or "AND". [0003] At present, a complementary metal oxide semiconductor (English: Complementary Metal Oxide Semiconductor, referred to as: CMOS) logic gate circuit is usually used to realize basic logic operations. The CMOS logic gate circuit includes a pull-up circuit and a pull-down circuit, wherein the pull-up circuit and the pull-down circuit All are composed of Metal-Oxide-Semiconductor Field-Effect Transistor (English: Metal-Oxide-Semiconductor Field-Effect Transistor, referred to as: MOSFET). However, since the MOSFET is limited by the Boltzmann distribution of carriers at room temperature, the subthreshold swing (English: subthreshold swing, SS for short) of the MOSFET cannot ...

AI Technical Summary

Problems solved by technology

However, since the TFET is a tunneling mechanism, the output curve is linear, which leads to the problem of a small driving current, and the small driving current makes it impossible to quickly change the level state of the output signal of the logic gate circuit, thus making the logic Gates have the problem of long delays

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