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Low-EMI deep trench isolation planar power semiconductor device and preparation method thereof

A power semiconductor and deep trench isolation technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve the problems of reducing device current density, increasing device cost, EMI interference, etc., to achieve Improve chip current density, reduce chip cost, and reduce the effect of terminal area

Active Publication Date: 2020-01-10
江苏芯长征微电子集团股份有限公司 +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

During packaging, since the drain electrode is welded on the package substrate, and the drain electrode is at a high potential, the drain electrode of the power semiconductor device is equivalent to the antenna effect, which will radiate the electromagnetic field outward and cause EMI interference;
[0017] 2) The terminal area adopts a field-limiting ring structure. This structure requires multiple rings to achieve a high breakdown voltage, and multiple rings will occupy a relatively large area, thereby reducing the current density of the device and increasing the cost of the device.

Method used

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  • Low-EMI deep trench isolation planar power semiconductor device and preparation method thereof
  • Low-EMI deep trench isolation planar power semiconductor device and preparation method thereof
  • Low-EMI deep trench isolation planar power semiconductor device and preparation method thereof

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Embodiment Construction

[0074] The present invention will be further described below in conjunction with specific drawings and embodiments.

[0075] In order to effectively reduce EMI interference, reduce chip area, reduce cost, and increase current density, taking N-type power semiconductor devices as an example, the present invention includes a semiconductor substrate 16 having an N conductivity type, in the center of the semiconductor substrate 16. The area is provided with a cell area and a terminal area located in the outer circle of the cell area; the cells in the cell area adopt a planar structure, and the cells in the cell area are connected in parallel on the front surface of the semiconductor substrate. The substrate source metal 30 is provided with a back electrode structure on the back of the semiconductor substrate 16;

[0076] On the cross section of the power semiconductor device, a P-type base region 26 of the substrate penetrating the terminal region is provided in the upper part of the t...

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Abstract

The invention relates to a power semiconductor device and a preparation method thereof, particularly relates to a low-EMI deep trench isolation planar power semiconductor device and a preparation method thereof, and belongs to the technical field of power semiconductor devices. Cells of a cell region are of a planar structure, terminal through hole isolation is used to replace an existing field limiting ring terminal structure, the terminal area is remarkably reduced, the chip cost is reduced, and the chip current density is improved. Substrate gate metal and a back electrode structure are placed on the back of a semiconductor substrate, and substrate source metal is located on the front of the semiconductor substrate. During packaging, the substrate source metal is welded to a packaging substrate, and the substrate gate metal and the back electrode structure are led out through routing. Because the substrate source metal is at a low potential, the packaging substrate is kept at a lowpotential, the effect of the package substrate emitting an electromagnetic field outwards is basically eliminated, and EMI (Electro-Magnetic Interference) is reduced.

Description

Technical field [0001] The invention relates to a power semiconductor device and a preparation method thereof, in particular to a low EMI deep trench isolation planar power semiconductor device and a preparation method thereof, and belongs to the technical field of power semiconductor devices. Background technique [0002] Power semiconductor devices work with relatively high voltage and current, used for energy conversion and transmission, and are generally used as switching devices. MOSFET is a field-effect unipolar conduction power semiconductor device, which controls the turn-on and turn-off between the source and drain through the gate. IGBT is a bipolar conductive power semiconductor device, which controls the conduction of the collector and emitter through the gate. The main difference between the N-type MOSFET device and the N-type MOSFET device is that the back side of the N-type IGBT device has P-type doping implantation, and the other structures are basically the same...

Claims

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Application Information

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IPC IPC(8): H01L29/06H01L21/336H01L29/78H01L23/552
CPCH01L29/78H01L29/66477H01L29/0615H01L23/552
Inventor 白玉明杨飞吴凯张广银朱阳军
Owner 江苏芯长征微电子集团股份有限公司