Imaging synchronous control system of multi-channel CMOS

Abstract

The invention discloses an imaging synchronous control system of a multi-channel CMOS, relates to an imaging synchronous control system of the multi-channel CMOS, and solves the problem that related clocks cannot be used for control due to the 8-time non-integral multiple relationship between the frequency of a clock and the Baud rate of a serial 422 in the conventional CMOS driving time sequence.For the application of a plurality of groups of imaging controllers, the problems of difficulty in image pickup synchronization among the imaging controllers and the like exist. Each imaging group outputs an independent row period signal for synchronous control of camera shooting; the 422 serial communication control module receives a 422 command sent by the camera controller. The time sequence driving control module generates a time sequence and a driving signal which meet voltage and current requirements. The imaging focal plane module is used for carrying out photoelectric conversion and generating a voltage and a bias signal required by the detector at the same time. The data conditioning and sending module is used for conditioning the multi-channel serial data and outputting data meeting a data transmission interface protocol. The data transmission interface module outputs a signal specified by a data transmission interface protocol. According to the invention, the shooting synchronism of each group can be ensured to the greatest extent.

Description

technical field [0001] The invention relates to a multi-channel CMOS imaging synchronous control system, in particular to a multi-channel CMOS imaging synchronous control method controlled by a daisy chain structure serial bus. Background technique [0002] The baud rate of serial transmission is not an integer multiple of the pixel clock frequency; for the timing driver module, since most ISERDES modules inside the FPGA cannot achieve 1:12 conversion even if they are cascaded, the 1:6 conversion Basically, an additional 1:2 conversion is required, so the clock frequency of the timing driver module is twice the pixel clock frequency. For serial communication, when the transmission baud rate is high and multi-point connection, in order to ensure reliable transmission, the control clock frequency is usually an integer multiple of 8 times the baud rate; this may cause the clock frequency of the timing driver module and The frequency of the control clock for serial communicatio...

AI Technical Summary

Problems solved by technology

[0005] The present invention solves the relationship between the frequency of the existing CMOS drive timing control clock and the 8 times non-integer multiple of the baud rate of the serial 422, resulting in the inability to use the relevant clock for control; for the application of multiple imaging controllers, there are various imaging Problems such as difficulty in camera synchronization between controllers

Images