3D Laminated Semiconductor Device

Abstract

The invention discloses a three-dimensional stacked semiconductor element, which comprises a substrate and a plurality of stacked structures formed on the substrate. Each stacked structure includes: a plurality of first conductive layers and a plurality of insulating layers alternately stacked on the substrate, and a second conductive layer. The first conductive layer is a first conductive type polysilicon layer and has a first width in the first direction. The second conductive layer is formed above the insulating layers, and the second conductive layer is a polysilicon layer of the second conductivity type and has a second width in the first direction, wherein the second width is equal to the first width.

Description

technical field [0001] The present invention relates to a three-dimensional stacked semiconductor device, and more particularly, to a three-dimensional stacked semiconductor device with a pad structure that can improve the landing of contact vias. Background technique [0002] A great feature of the design of non-volatile memory elements is that they preserve the integrity of the data state when the memory element loses or removes power. At present, many different types of non-volatile memory elements have been proposed in the industry. However, related industries are still developing new designs or combining existing technologies to stack memory cell planes to achieve a memory structure with higher storage capacity. For example, some three-dimensional stacked NAND (NAND) type flash memory semiconductor devices have been proposed. However, conventional three-dimensional stacked semiconductor devices still have some problems to be solved. [0003] For example, in a convent...

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Problems solved by technology

However, conventional three-dimensional stacked semiconductor devices still have some problems to be solved

[0003] For example, in a conventional three-dimensional stacked semiconductor device, the polysilicon channel layer extends above the stacked structure for contact vias (such as bit line contact vias) to land, but the thickness of the polysilicon channel layer is too thin to increase the difficulty of landing , and has the disadvantage of rising resistance

In the traditional process, additional N+ ion implantation is generally required to reduce the resistance

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