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Memory protection method based on RISC-V

A RISC-V and memory technology, applied in the protection of internal/peripheral computer components, instruments, electrical digital data processing, etc., can solve the problems of no memory protection, data privacy and security threats, etc., to ensure data privacy and Security, the effect of preventing memory from being accessed and tampered with by malicious programs

Inactive Publication Date: 2020-03-27
SICHUAN PANOVASIC TECH
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Problems solved by technology

[0003] The purpose of the present invention is to provide a RISC-V-based memory protection method, which is used to solve the problem that the embedded device has no protection for the memory in the prior art, and the application can access all areas of the memory, which poses a threat to the privacy and security of data. question

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  • Memory protection method based on RISC-V
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Embodiment 1

[0025] combined with figure 1 As shown, a RISC-V-based memory protection method includes:

[0026] Step 1. The RISC-V chip device has developed n APP applications, and there is interaction between APP applications;

[0027] Step 2. Divide the memory area of ​​the RISC-V chip into n+1 mutually independent areas. The first n areas correspond to n APP applications, and the n+1th area is a shared memory area, which can be accessed by any APP application. , the shared memory area is used for data interaction between APP applications;

[0028] Step 3, configure the RISC-V privileged instruction set, the memory control register configuration application APP1 has access rights to memory area 1 and memory area n+1 as RWX=111 (R indicates degree authority, W indicates write authority, and X indicates executable authority , 1 means permission, 0 means no permission), the access right to other remaining memory is RWX=000;

[0029] Step 4. Configure the RISC-V privileged instruction set...

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Abstract

The invention discloses a memory protection method based on RISC-V. The memory protection method based on RISC-V comprises the following steps: S1, developing n APP applications by adopting equipmentof an RISC-V chip; S2, dividing a memory of the RISC-V chip into n mutually independent memory regions, wherein the n memory regions respectively correspond to n APP applications; and S3, configuringan RISC-V privileged instruction set, and configuring each application APP in the memory control register, so that each application APP has access permission in the corresponding memory area and has no access permission in other memory areas. According to the memory protection method, the memory area of the RISC-V is controlled in a blocking manner, so that the memory is effectively prevented frombeing accessed and tampered by malicious programs; and each application of the RISC-V equipment independently accesses the memory area in the respective authority without mutual interference, so thatthe data privacy and security are ensured.

Description

technical field [0001] The present invention relates to the technical field of information security, in particular to the technical field of embedded memory security, and specifically relates to a RISC-V-based memory protection method. Background technique [0002] With IoT devices now connected to the Internet, on-device security has become even more important, especially for secure applications. At present, the memory of almost all embedded devices without MMU (Memory Manage Unit) is not protected, and all applications on the device can access all areas of the memory, which gives the privacy and security of application data poses threats and challenges. Contents of the invention [0003] The purpose of the present invention is to provide a RISC-V-based memory protection method, which is used to solve the problem that the embedded device has no protection for the memory in the prior art, and the application can access all areas of the memory, which poses a threat to the ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F21/78
CPCG06F21/78G06F2221/2141
Inventor 杨国东刘建敏杨超周强强翟栋
Owner SICHUAN PANOVASIC TECH