Simulation signal checking method and system for digital product

Abstract

The invention discloses a simulation signal checking method for a digital product and a simulation system. The simulation signal checking method comprises the steps: reading and recording the state data of all external ports of the digital product in real time when FPGA simulation is carried out on the digital product, and reading and recording all internal state data of the digital product at setintervals; after completing simulation, when the data of a certain clock period of the digital product needs to be traced back and checked, in the recorded simulation data, reading the internal statedata of the digital product and the external port state data of the time point stored at the last time point before the clock period at the moment; and taking the read data as initial running state data of the FPGA, and then reading all internal state data of the digital product one by one in a clock manner until the digital product runs to a clock period required to be checked. By adopting the technical scheme of the invention, all simulation data of any clock period can be quickly backtracked and checked.

Description

technical field [0001] The invention relates to the field of simulation of digital logic products, in particular to a method and system for viewing simulation signals of digital products. Background technique [0002] In the design process of digital logic products, it is necessary to use simulation verification to test and verify the correctness of the design. Generally speaking, this link is completed by using a software simulator (Simulator). [0003] The working principle of the software simulator is: run the design under test (RTL code or gate-level netlist) and test vector (HVL code or non-synthesizable SystemVerilog program) in the simulator, and interact with the interface signals of the design under test and the test vector, Complete the verification process defined in the test vector. Developers can check the value of any test vector, view the value of any port or internal signal of the design under test, or the waveform composed of multiple clock cycles to confir...

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Problems solved by technology

[0013] The purpose of the present invention is to provide a method for viewing simulation signals of digital products that can quickly retrospectively view all simulation data of any clock cycle in view of the technical problem that the general-purpose FPGA realizes signal full visibility at a slow and time-consuming technical problem in the above-mentioned prior art. and system

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