Power switch control circuit, memory device and method for controlling power switch

Abstract

The power switch control circuit includes a power rail configured to provide power to the memory array. A first headswitch couples the power rail to a first power supply corresponding to a first power supply domain. A second headswitch couples the power rail to a second power supply corresponding to a second power supply domain. The control circuit is configured to receive the select signal and the close signal, and output a control signal to the first head switch and the second head switch in response to the select signal and the close signal to selectively turn the first head switch and the second head switch coupled to the first power supply and the second power supply, respectively. The control circuit is configured to output a control signal to the first head switch and the second head switch to connect the first head switch and the second head switch to the first power source and the second head switch in response to the off signal and regardless of the select signal. 2. The power supply is disconnected. Embodiments of the invention also relate to memory devices and methods of controlling power switches.

Description

technical field [0001] Embodiments of the present invention relate to a power switch control circuit, a memory device, and a method of controlling a power switch. Background technique [0002] Some known memory devices, such as static random access memory (SRAM) devices, include power switch control designs. A typical SRAM memory device has an array of memory cells. Each memory cell uses six transistors connected between an upper reference potential and a lower reference potential (usually ground), so that one of the two storage nodes can be occupied by information to be stored, with complementary information stored in the other on the storage node. Some SRAM arrangements operate memory logic in a low voltage domain, while memory arrays operate in a high voltage domain. Additionally, various techniques can be employed to reduce power consumption. For example, a portion of the memory device may be turned off during a sleep or shutdown mode. Problems can arise if the swit...

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Problems solved by technology

Additionally, direct current (DC) leakage between the headswitches can lead to large off-leakage in off-mode when only the internal headswitches are turned off

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