An integrated circuit computing device and computing processing system

Abstract

The invention discloses an integrated circuit computing device, comprising: a first processing module for receiving and processing an RISC-V instruction set instruction; a second processing module connected with the first processing module; a first bus connected with the first processing module and the second processing module, and connected with a first port of the first processing module and a second port of the second processing module. According to the embodiment of the invention, a RISC-V architecture processor hard core is embedded into an FPGA chip, so that FPGA chip developers can flexibly adjust the processor hard core as required, the computing power of the FPGA chip is enhanced, and small equipment area, low power consumption and low manufacturing cost are ensured.

Description

technical field [0001] The invention belongs to the field of system-level chip design, and in particular relates to an integrated circuit computing device and a computing processing system. Background technique [0002] At present, in FPGA (Field Programmable Gate Array, Field Programmable Gate Array) design, processor hard core or soft core is usually embedded, that is, an ASIC (Application Specific Integrated Circuit, Application Specific Integrated Circuit) that embeds a processor inside the FPGA chip. The circuit implements a processor on the programmable logic of the FPGA in the form of HDL (Hardware Description Language, hardware description language) program code. [0003] However, FPGAs with embedded processor hard cores are commercial IP cores such as ARM (Advanced RISC Machine) and PowerPC. The use of commercial IP will greatly increase the cost of FPGA users. On the one hand, FPGA On the other hand, when users want to convert the design on FPGA to ASIC (Applicati...

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Problems solved by technology

[0003] However, FPGAs with embedded processor hard cores are commercial IP cores such as ARM (Advanced RISC Machine) and PowerPC. The use of commercial IP will greatly increase the cost of FPGA users. On the one hand, FPGA On the other hand, when users want to convert the design on FPGA to ASIC (Application Specific Integrated Circuit, application specific integrated circuit) design, they still need to pay extra IP usage fees; secondly, most commercial IP cores (Intellectual Property core )’s internal design details are invisible, which cannot meet the requirements of some application scenarios that require the chip to be completely safe and controllable (such as security scenarios such as national defense and military industry); third, the design flexibility of commercial IP is poor. For a certain type of IP, subsequent product upgrades will be limited by IP capabilities

However, FPGAs using soft cores need to occupy logic resources on the FPGA when the soft cores are implemented, and compared with hard cores, they consume large power consumption, large area, and low computing power, so they cannot meet high-precision, high-real-time applications. demand, less practical

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