Atomic layer etching method for semiconductor processing
An atomic layer etching and semiconductor technology, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as excessive etching and insufficient etching of local topography, so as to avoid insufficient etching of local topography or The effect of over etching
Active Publication Date: 2020-06-05
BEIJING NAURA MICROELECTRONICS EQUIP CO LTD
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Problems solved by technology
[0003] The present invention proposes an atomic layer etching method for semiconductor processing to solve the problems in the background technology, for example, if the atomic layer etching technology continues to Etching relatively rough surface topography may lead to insufficient or over-etching of local topography in subsequent steps
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[0033] The following disclosure provides various implementations or illustrations, which can be used to achieve different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. It will be appreciated that these descriptions are merely examples and are not intended to limit the disclosure. For example, in the description below, forming a first feature on or over a second feature may include some embodiments wherein the first and second features are in direct contact with each other; and may also include In some embodiments, additional components are formed between the first and second features, such that the first and second features may not be in direct contact. In addition, this disclosure may reuse reference symbols and / or labels in various embodiments. Such repetition is for the sake of brevity and clarity, and does not in itself represent a relationship between the different embodiments and / or ...
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The invention discloses an atomic layer etching method for semiconductor processing. The atomic layer etching method comprises: a surface atomic deposition step: introducing etching gas into a reaction chamber to combine the etching gas with surface atoms of a wafer; a surface repairing step: introducing a repairing gas to enable the repairing gas to adsorb the surface atoms, wherein the components of the repairing gas are the same as partial elements for manufacturing the wafer; adjusting the temperature of a lower electrode for bearing the wafer to adjust the temperature of the wafer so as to move the surface atoms to flatten the surface of the wafer; and a surface atom desorption step: increasing the energy of the surface atoms to desorb the surface atoms from the wafer so as to etch the wafer. According to the method, surface atom repair is added after surface atom deposition and surface atom desorption, so that the rough surface morphology is repaired, and the problem of insufficient local morphology etching or excessive etching caused by continuous etching of the rough surface morphology is avoided.
Description
technical field [0001] The present invention relates to the field of semiconductors, in detail, relates to an atomic layer etching method for semiconductor processing. Background technique [0002] With the development of integrated circuit technology, the size of integrated circuits is gradually reduced, and the requirements for shape control accuracy in the process are getting higher and higher. Therefore, atomic-level precision patterned etching of material topography may be required. In response to this demand, the atomic layer etching technology based on the surface self-limiting effect has been widely researched and applied. In the atomic layer etching technology, surface atom deposition and surface atom desorption are repeatedly performed on the wafer to achieve the effect of atomic layer etching. However, in each surface atom deposition and surface atom desorption step, it is equivalent to forming a relatively rough surface topography on the wafer surface. If the ...
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IPC IPC(8): H01L21/223H01L21/263
CPCH01L21/2633H01L21/223
Inventor 刘珂蒋中伟
Owner BEIJING NAURA MICROELECTRONICS EQUIP CO LTD