Debugging system and method for power-on crash of chip

A debugging system and electric crash technology, applied in the field of integrated circuits, can solve the problems of difficult chip debugging, high manpower and time costs, and achieve the effect of saving material costs, saving manpower and time costs, and achieving realizability

Active Publication Date: 2020-06-16
HUNAN GOKE MICROELECTRONICS
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The number of internal signals observed in the first method can be set to multiple, but software cooperation configuration registers are required to implement debugging; the second method does not require software cooperation configuration registers compared to the first method, but spe

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  • Debugging system and method for power-on crash of chip
  • Debugging system and method for power-on crash of chip
  • Debugging system and method for power-on crash of chip

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[0076] The core of the present invention is to provide a debugging system and method for chip power-on crash, which is used to solve the feasibility of debugging when the chip power-on crashes and save the debugging cost.

[0077] In order to make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be described clearly and completely in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of the embodiments of the present invention, not all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.

[0078] The structure diagram of the internal debugging method of the existing chip is as figure 1 Shown in figure ...

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Abstract

The invention discloses a debugging system and a debugging method for power-on crash of a chip, which are used for solving the debugging realizability during power-on crash of the chip and saving thedebugging cost. The debugging system comprises a guide pin configuration module, a debugging multipath selection module, a latch module and a debugging module, wherein the guide pin configuration module is connected with a control end of the debugging multipath selection module and the latch module through using guide pins, and the latch module is connected with the debugging module; the guide pinconfiguration module is used for configuring level information of guide pins and controlling the debugging multipath selection module to establish a debugging path when the chip encounters power-on crash and enters a debugging mode; the latch module is used for latching the level information of the guide pins when the chip is reset; and the debugging module is used for acquiring the level information of the guide pins from the latch module when the chip enters a normal working mode, and determining a debugging path according to the level information of the guide pins.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a debugging system and method for on-chip electrical crashes. Background technique [0002] As chip integration logic becomes more and more complex and the cost is higher and higher, the more means of chip debugging (debugging), the better. For example, the problem of power-on crash is fatal, but it is extremely difficult to debug because there are too few observation points. For example, it is known that in a certain project, the central processing unit (CPU) starts to execute the Read-Only Memory (ROM) instruction when it is powered on, because the ROM has an instruction that hangs, causing the system chip to crash when it is powered on, and the existing debugging methods cannot be used. Expand. Finally, through chip code tracing and automatic test equipment (ATE) testing, the bug point is located. The bug point is: the parameters programmed by One Time Programmab...

Claims

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Application Information

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IPC IPC(8): G01R31/317
CPCG01R31/31705Y02D10/00
Inventor 亓磊
Owner HUNAN GOKE MICROELECTRONICS
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