Debugging system and method for power-on crash of chip
A debugging system and electric crash technology, applied in the field of integrated circuits, can solve the problems of difficult chip debugging, high manpower and time costs, and achieve the effect of saving material costs, saving manpower and time costs, and achieving realizability
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[0076] The core of the present invention is to provide a debugging system and method for chip power-on crash, which is used to solve the feasibility of debugging when the chip power-on crashes and save the debugging cost.
[0077] In order to make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be described clearly and completely in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of the embodiments of the present invention, not all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.
[0078] The structure diagram of the internal debugging method of the existing chip is as figure 1 Shown in figure ...
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