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Scalar cell with high-performance cryptographic operation

A technology of scalar and cryptographic algorithms, applied in the field of providing enhanced scalar operations, which can solve problems such as weak performance

Inactive Publication Date: 2020-06-16
NANJING ILUVATAR COREX TECH CO LTD (DBA ILUVATAR COREX INC NANJING)
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

On the other hand, typical scalar units in GPGPU devices have relatively weak performance compared to vector units when it comes to cryptographic operations and requirements

Method used

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  • Scalar cell with high-performance cryptographic operation
  • Scalar cell with high-performance cryptographic operation
  • Scalar cell with high-performance cryptographic operation

Examples

Experimental program
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Embodiment Construction

[0016] The present invention can now be described more fully with reference to the accompanying drawings, which form a part of the present invention and show in diagrammatic manner specific exemplary embodiments in which the present invention can be implemented. These illustrations and exemplary embodiments may be presented with the understanding that the present disclosure is an illustration of the principles of one or more inventions, and may not be intended to limit any one invention to the illustrated embodiments. The present invention can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein; on the contrary, these embodiments are provided so that this disclosure will be comprehensive and complete, and the scope of the present invention will be fully conveyed to the art Technical staff. In addition, the present invention can be embodied as a method, system, computer readable medium, device or device. Theref...

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Abstract

Embodiments of the present invention provide a technical solution by varying scalar units to enable it to be used in high performance cryptographic applications. Aspects of the present disclosure provide a scalar cell having four 32-bit arithmetic logic units (ALUs). The four ALUs may independently serve as four separate lanes, each lane generating a 32-bit result. Accordingly, the number of instructions (IPC) completed per cycle may be four. Furthermore, the four sets of 32-bit ALUs may be configured as two 64-bit ALUs, with every two 32-bit ALUs as a set. In one embodiment, the configurationmay generate two 64-bit results per cycle. In addition, when the ALUs are combined into a single unit, the four groups of 32-bit ALUs can be configured into a 128-bit ALU. Aspects of the invention generate an output having a data width or format different from 32 bits from a set of four 32-bit scalar ALUs.

Description

Technical field [0001] Embodiments of the present invention generally relate to providing enhanced scalar operations. Background technique [0002] Vector processing in a processor such as a central processing unit (CPU) or graphics processing unit (GPU) executes an instruction set, which contains instructions for operating on a one-dimensional data array called a vector. This is in contrast to scalar processors, whose instructions operate on a single data item. [0003] Vector instructions usually perform operations on each data element in consecutive cycles. The vector function unit in the instruction is pipelined. In addition, each pipeline stage operates on a piece of data, and there is no vector dependency (internal and between vectors). [0004] However, there are disadvantages, especially when vector operations are irregular. At the same time, if the memory operation balance is not monitored and maintained, and the data is not correctly or properly mapped to the appropriat...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/30
CPCG06F9/3001G06F21/602G06T1/20H04L2209/12H04L9/0618H04L9/0643G06F9/30014
Inventor 邵平平骆培李成
Owner NANJING ILUVATAR COREX TECH CO LTD (DBA ILUVATAR COREX INC NANJING)