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Encapsulation method

A packaging method and packaging structure technology, which is applied in the direction of semiconductor devices, electrical components, circuits, etc., can solve the problems that the performance of the packaging structure needs to be improved, and achieve the effect of improving the packaging effect, performance, electrical performance and reliability

Active Publication Date: 2022-05-10
NINGBO SEMICON INT CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The performance of the packaging structure formed by the packaging method of the prior art still needs to be improved

Method used

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Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0013] It can be seen from the background art that the performance of the packaging structure manufactured by the existing packaging method needs to be improved.

[0014] An analysis is now combined with a packaging method, and the packaging method is regarded as fan-out wafer-level packaging. figure 1 and figure 2 It is a schematic cross-sectional structure diagram of a fan-out wafer-level packaging process, and the packaging method includes the following steps:

[0015] refer to figure 1 , provide a substrate 10, the substrate 10 has a plurality of chips 20, and the chip 20 has an electrical connection structure 30, the surface of the chip 20 exposes the surface of the electrical connection structure 30, and the connection between adjacent chips 20 A plastic encapsulation layer 40 is formed on the substrate 10 ; a buffer layer 50 is formed on the surface of the chip 20 and the surface of the plastic encapsulation layer 40 , and the buffer layer 50 exposes the surface of t...

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Abstract

The invention provides a packaging method, including: providing a structure to be packaged, the structure to be packaged includes a plurality of chips and a plastic sealing layer between adjacent chips, the chip has a front surface and a back surface opposite to the front surface, and a chip is formed in the chip. There is an electrical connection structure, the front of the chip exposes the electrical connection structure, and the structure to be packaged has a plurality of contact areas and a buffer zone between adjacent contact areas; selective spraying treatment is carried out to the front of the chip of the buffer zone and the plastic packaging The slurry is sprayed on the surface of the buffer layer, and the slurry in the buffer zone is cured to form a buffer layer in the buffer layer, which exposes the surface of the electrical connection structure; on the surface of the buffer layer and the surface of the electrical connection structure in the contact area A rewiring layer is formed, the rewiring layer is electrically connected to the electrical connection structure. The invention forms the buffer layer by selective spraying treatment, reduces the damage caused by the process of forming the buffer layer, and further improves the reliability of the formed packaging structure.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a packaging method. Background technique [0002] With the development trend of very large scale integrated circuits, the feature size of integrated circuits continues to decrease, and people's requirements for packaging technology of integrated circuits continue to increase accordingly. Existing packaging technologies include ball grid array packaging (Ball GridArray, BGA), chip size packaging (Chip Scale Package, CSP), wafer level packaging (Wafer Level Package, WLP), three-dimensional packaging (3D) and system packaging (Systemin Package). , SiP) etc. [0003] The redistribution layer (redistribution layer, RDL) is one of the important technical branches in the packaging technology. The rewiring layer mainly refers to depositing metal layers and dielectric layers on the surface of the wafer and forming corresponding metal wiring patterns to re-layout the inpu...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/56H01L21/60
CPCH01L21/56H01L24/43
Inventor 秦晓珊
Owner NINGBO SEMICON INT CORP