Hybrid high-voltage low-voltage finfet device

Abstract

An integrated circuit includes a plurality of low-voltage FinFET transistors each having a channel length l and a channel width w, the low-voltage FinFET transistors having a first threshold voltage channel implant and a first gate dielectric thickness. The integrated circuit also includes a plurality of high-voltage FinFET transistors each having the channel length / and the channel width w, thehigh-voltage FinFET transistors having a second threshold voltage channel implant greater than the first threshold voltage channel implant and second gate dielectric thickness greater than the first gate dielectric thickness.

Description

Background technique [0001] The present invention relates to field effect transistors (FETs). More specifically, the present invention relates to FinFET transistors. [0002] Static random access memory (SRAM) field programmable gate array (FPGA) integrated circuits traditionally use common NMOS planar transistor devices as switches. There are two problems with these transistor devices. Switches exhibit source-drain leakage when they are off. Furthermore, such switches offer reduced performance compared to CMOS transfer gate switching devices because they do not pass the full V DD Voltage. [0003] In processes utilizing the 90nm minimum feature size, at least one SRAM FPGA manufacturer has introduced custom transistors that are not devices typically available in standard fabrication processes. The device has a thicker oxide and can be overdriven at its gate above V DD operate under the circumstances. These transistors are called "medium oxide" because they have a gate ...

AI Technical Summary

Problems solved by technology

Ultimately, the channel length can only be adjusted in a quantitative manner, and only without increasing the pitch of the transistors (which would otherwise cause a large pitch penalty)

FinFET process and lithography pitch rules limited by making 14nm geometries with 193nm light

Images