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A kind of preparation method of double-layer epitaxy for MOS device structure

A MOS device and double-layer epitaxy technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as difficulty in controlling the consistency of resistivity distribution

Active Publication Date: 2022-04-12
CHINA ELECTRONICS TECH GRP NO 46 RES INST +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] The purpose of the present invention is to overcome the difficulty in controlling the thickness distribution and resistivity distribution uniformity of the double-layer epitaxy used in the existing MOS devices during the long-term growth process. Allocation, a preparation method for double-layer epitaxy for MOS device structures, which significantly improves the consistency of thickness distribution and resistivity distribution after double-layer epitaxy

Method used

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  • A kind of preparation method of double-layer epitaxy for MOS device structure
  • A kind of preparation method of double-layer epitaxy for MOS device structure
  • A kind of preparation method of double-layer epitaxy for MOS device structure

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Experimental program
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Effect test

Embodiment 1

[0031] (1) Hydrogen chloride gas is introduced into the reaction chamber of the silicon epitaxy furnace, and the flow rate of the hydrogen chloride gas is set to 18 L / min. Set as 1160 ℃, etching time is set as 130 sec;

[0032] (2) Set the hydrogen flow rate of the main process to 75 L / min, carry gaseous trichlorosilane into the reaction chamber of the silicon epitaxy furnace, set the flow rate of trichlorosilane to 13.5 L / min, and the deposition time on the pedestal set to 20 sec;

[0033] (3) Load the silicon substrate on the base in the reaction chamber, raise the temperature to 1160 °C, bake the surface of the silicon substrate for 1 min and then lower the temperature to 1125 °C;

[0034] (4) Purge the reaction chamber with hydrogen gas from the main process, the hydrogen flow rate of the main process is 75 L / min, and the purging time is set to 30 sec;

[0035] (5) The flow rate of hydrogen in the main process is set at 65 L / min, carrying gaseous trichlorosilane into the...

Embodiment 2

[0043] (1) Hydrogen chloride gas is introduced into the reaction chamber of the silicon epitaxy furnace, and the flow rate of the hydrogen chloride gas is set to 18 L / min. Set as 1160 ℃, etching time is set as 130 sec;

[0044] (2) Set the hydrogen flow rate of the main process to 75 L / min, carry gaseous trichlorosilane into the reaction chamber of the silicon epitaxy furnace, set the flow rate of trichlorosilane to 13.5 L / min, and the deposition time on the pedestal set to 20 sec;

[0045] (3) Put the silicon substrate on the base in the reaction chamber, raise the temperature to 1160 °C, bake the surface of the silicon substrate for 1~2 minutes, and then lower the temperature to 1125 °C;

[0046] (4) Purge the reaction chamber with hydrogen gas from the main process, the hydrogen flow rate of the main process is 75 L / min, and the purging time is set to 30 sec;

[0047] (5) The flow rate of hydrogen in the main process is set to 85 L / min, and the gaseous trichlorosilane is ...

Embodiment 3

[0055] (1) Hydrogen chloride gas is introduced into the reaction chamber of the silicon epitaxy furnace, and the flow rate of the hydrogen chloride gas is set to 18 L / min. Set as 1160 ℃, etching time is set as 130 sec;

[0056] (2) Set the hydrogen flow rate of the main process to 75 L / min, carry gaseous trichlorosilane into the reaction chamber of the silicon epitaxy furnace, set the flow rate of trichlorosilane to 13.5 L / min, and the deposition time on the pedestal set to 20 sec;

[0057] (3) Load the silicon substrate on the base in the reaction chamber, raise the temperature to 1160 °C, bake the surface of the silicon substrate for 1 min and then lower the temperature to 1125 °C;

[0058] (4) Purge the reaction chamber with hydrogen gas from the main process. The hydrogen flow rate of the main process is 85 L / min, and the purging time is set to 30 sec;

[0059] (5) The flow rate of hydrogen in the main process is set to 85 L / min, and the gaseous trichlorosilane is carrie...

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Abstract

The invention relates to a preparation method of double-layer epitaxy for a MOS device structure. Hydrogen chloride gas is introduced into the reaction chamber of a silicon epitaxy furnace; the main process hydrogen carries gaseous trichlorosilane into the reaction chamber of the silicon epitaxy furnace; A silicon substrate is placed on the base; the main process hydrogen is introduced to purge the reaction chamber; the main process hydrogen carries gaseous trichlorosilane into the reaction chamber; the diluted hydrogen carries phosphine gas to form a mixed gas; the first layer The growth of the silicon epitaxial layer; the main process hydrogen is introduced to purge the reaction chamber of the silicon epitaxial furnace; the growth of the second layer of silicon epitaxial layer is carried out; the growth of the second layer of silicon epitaxial layer is completed, and it is taken out from the base after cooling down; The 5-point average value of the total thickness of the silicon epitaxial layer is 20.5~21.5µm, and the 5-point average value of the resistivity of the second silicon epitaxial layer is 27~29Ω·cm. The invention realizes the control of the overall thickness and resistivity uniformity of double-layer epitaxy.

Description

technical field [0001] The invention relates to the technical field of preparation of semiconductor epitaxy materials, in particular to a preparation method of double-layer epitaxy for MOS device structures. Background technique [0002] MOS devices aim at high breakdown voltage and low forward conduction voltage drop. The traditional planar MOS device structure is based on a single-layer silicon epitaxial wafer, which consists of a low-resistance silicon substrate and a high-resistance silicon epitaxial layer. In order to ensure the high breakdown voltage requirements of MOS devices, it is necessary to use a thick and high-resistance silicon epitaxial layer, but this will lead to an increase in the conduction voltage drop. Contradiction, that is, if the breakdown voltage increases, the conduction voltage drop will also increase accordingly. Therefore, the conduction voltage drop is limited by the breakdown voltage and there is a limit. In recent years, in order to furthe...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/205H01L21/336
CPCH01L21/02381H01L21/02532H01L21/0257H01L21/02634H01L21/02658H01L21/0262H01L29/66477
Inventor 唐发俊李明达王楠赵扬
Owner CHINA ELECTRONICS TECH GRP NO 46 RES INST