Method for obtaining matrix decomposition time based on machine learning training model

Abstract

The invention discloses a method for obtaining matrix decomposition time based on a machine learning training model. The method comprises the following steps of 1) obtaining a circuit matrix data set,2) carrying out matrix decomposition time model training according to the data set, and 3) predicting the matrix decomposition time of an unknown circuit according to the matrix decomposition time model obtained by training. The method for obtaining the matrix decomposition time based on the machine learning training model can predict the matrix decomposition time, reasonably allocate computing resources, shorten the circuit simulation time and improve the circuit simulation efficiency.

Description

technical field [0001] The invention relates to the technical field of EDA circuit simulation, in particular to a method for predicting circuit matrix decomposition time in circuit simulation. Background technique [0002] With the increase of integrated circuit integration, the circuit complexity is also increasing day by day. In the existing Integrated Circuit / Computer Aided Design (Integrated Circuit / Computer Aided Design), using general-purpose circuit simulation program analysis, for VLSI, it takes a lot of Especially when performing transient analysis, multiple iterations are required to decompose the circuit matrix, and the calculation amount of the simulation tool will also explode. At present, VLSI is faced with too many calculations, unbalanced allocation of computing resources, and long simulation time, which also seriously affect the designer's design cycle. [0003] Because the circuit matrix decomposition needs to be iterated many times, it needs a lot of comp...

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Problems solved by technology

[0002] With the increase of integrated circuit integration, the circuit complexity is also increasing day by day. In the existing Integrated Circuit / Computer Aided Design (Integrated Circuit / Computer Aided Design), using general-purpose circuit simulation program analysis, for VLSI, it takes a lot of The computer time, especially when performing transient analysis, requires multiple iterations to decompose the circuit matrix, making the calculation amount of simulation tools also explode

At present, VLSI is faced with a large amount of calculation, unbalanced allocation of computing resources, and long simulation time, which seriously affect the designer's design cycle.

[0003] Because the circuit matrix decomposition needs to be iterated many times, it needs a lot of computing resources, but before the circuit simulation, it is not possible to know how many computing resources are needed, which often leads to unbalanced distribution of computing resources, resulting in long simulation time and waste of computing resources.

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