A Method of Obtaining Matrix Decomposition Time Based on Machine Learning Training Model

Abstract

A method for obtaining matrix decomposition time based on a machine learning training model, comprising the following steps: 1) obtaining a circuit matrix data set; 2) performing matrix decomposition time model training according to the data set; 3) obtaining a matrix decomposition time model according to the training , to predict the matrix factorization time for an unknown circuit. The method for obtaining matrix decomposition time based on a machine learning training model of the present invention can estimate the matrix decomposition time, rationally allocate computing resources, shorten circuit simulation time, and improve circuit simulation efficiency.

Description

Technical field [0001] The present invention relates to the field of EDA circuit simulation technology, in particular to a method of predicting the decomposition time of the circuit matrix in circuit simulation. Background [0002] With the increase in the integration of integrated circuits, the complexity of circuits is also increasing day by day, in the existing integrated circuit computer-aided design (Integrated Circuit / Computer Aided Design), the use of general circuit simulation program analysis, for ultra-large scale integrated circuits, the need to consume a lot of machine, especially in the transient analysis need to carry out multiple iterations to decompose the circuit matrix, so that the simulation tool calculation amount will also explode. At present, the amount of computation faced by the current ultra-large scale integrated circuit, the uneven allocation of computing resources, and the long simulation time also seriously affect the design cycle of designers. [0...

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Problems solved by technology

[0002] With the increase of integrated circuit integration, the circuit complexity is also increasing day by day. In the existing Integrated Circuit / Computer Aided Design (Integrated Circuit / Computer Aided Design), using general-purpose circuit simulation program analysis, for VLSI, it takes a lot of The computer time, especially when performing transient analysis, requires multiple iterations to decompose the circuit matrix, making the calculation amount of simulation tools also explode

At present, VLSI is faced with a large amount of calculation, unbalanced allocation of computing resources, and long simulation time, which seriously affect the designer's design cycle.

[0003] Because the circuit matrix decomposition needs to be iterated many times, it needs a lot of computing resources, but before the circuit simulation, it is not possible to know how many computing resources are needed, which often leads to unbalanced distribution of computing resources, resulting in long simulation time and waste of computing resources.

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