Inverter circuit and method for preventing ARM SHORT phenomenon
An inverter circuit and phenomenon technology, applied in the field of inverter circuits to prevent the ARMSHORT phenomenon, can solve problems affecting circuit design, imperfection, up and down direct connection, etc., to avoid product damage and defects, strong anti-interference performance, and stability and high safety effect
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Embodiment 1
[0059] like Figure 5 , The inverter circuit of the present invention is an IGBT half-bridge inverter circuit.
[0060]The inverter circuit in this embodiment includes a half-bridge module 100 , a capacitor bank 200 and an inductor 300 . The half-bridge module 100 includes an upper bridge arm 101 , a lower bridge arm 102 and a clamping circuit 103 disposed therebetween. The upper bridge arm 101 includes a first voltage-driven device 101 a and a first diode 101 b connected in antiparallel with it. The lower bridge arm 102 includes a second voltage-driven device 102a and a second diode 102b. The clamping circuit 103 includes a third diode 103a connected between the first voltage-driven device 101a and the second voltage-driven device 102a.
[0061] Both the first voltage-driven device 101a and the second voltage-driven device 102a are insulated gate bipolar transistors, wherein the first electrode of the insulated gate bipolar transistor is its gate, and the first pole of the...
Embodiment 2
[0065] like Image 6 , The inverter circuit of the present invention is a MOSFET half-bridge inverter circuit.
[0066] The inverter circuit in this embodiment includes a half-bridge module 100 , a capacitor bank 200 and an inductor 300 . The half-bridge module 100 includes an upper bridge arm 101 , a lower bridge arm 102 and a clamping circuit 103 disposed therebetween. The upper bridge arm 101 includes a first voltage-driven device 101 a and a first diode 101 b connected in antiparallel with it. The lower bridge arm 102 includes a second voltage-driven device 102a and a second diode 102b. The clamping circuit 103 includes a third diode 103a connected between the first voltage-driven device 101a and the second voltage-driven device 102a.
[0067] Both the first voltage-driven device 101a and the second voltage-driven device 102a are N-channel metal-oxide semiconductor field-effect transistors (referred to as metal-oxide-semiconductor field-effect transistors), wherein the ...
Embodiment 3
[0071] like Figure 7 , The inverter circuit of the present invention is a P / N channel MOSFET half-bridge inverter circuit.
[0072] The inverter circuit in this embodiment includes a half-bridge module 100 , a capacitor bank 200 and an inductor 300 . The half-bridge module 100 includes an upper bridge arm 101 , a lower bridge arm 102 and a clamping circuit 103 disposed therebetween. The upper bridge arm 101 includes a first voltage-driven device 101 a and a first diode 101 b connected in antiparallel with it. The lower bridge arm 102 includes a second voltage-driven device 102a and a second diode 102b. The clamping circuit 103 includes a third diode 103a connected between the first voltage-driven device 101a and the second voltage-driven device 102a.
[0073] The first voltage-driven device 101a is a P-channel field effect transistor, and the second voltage-driven device 102a is an N-channel field effect transistor. The first pole of both is its gate, and the second pole o...
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