FPGA optimization method and system for star topology structure of maintenance system

Abstract

The invention discloses an FPGA optimization method and system for a star topology structure of a maintenance system. The method comprises the steps: S100, adding a maintenance relay module in each FPGA fragment in a plurality of FPGA fragments, enabling the maintenance relay module to be connected with a core functional module, and enabling the original single-shot logic to be changed into multi-shot logic; and S200, based on the maintenance relay modules in the plurality of FPGA fragments, converting a connection structure between the plurality of FPGA fragments and the maintenance system functional module from a star topology structure to a serial structure. According to the invention, a star topology structure is converted into a serial structure, so that the interconnection problem ofa plurality of FPGAs of a maintenance system under a multi-core scale is solved; the maintenance relay module is added, the original single-beat logic is changed into multi-beat logic, and the trigger is used for beating the threading logic twice, so that the problem of timing convergence of the threading logic is solved.

Description

technical field [0001] The invention relates to the field of FPGA optimization, in particular to an FPGA optimization method and system for maintaining a system star topology. Background technique [0002] Usually in chip design, in order to facilitate maintenance and debugging, maintenance system function modules are designed. [0003] With SoC multi-core technology [0004] With rapid development, the number of cores integrated on a chip is increasing, and the scale is also increasing. The maintenance system in a multi-core chip usually adopts a star topology, and the maintenance system function modules and all core modules inside the chip are connected. Used for maintenance diagnostic test logic such as scanning and error reporting. [0005] When performing FPGA simulation verification, after FPGA fragmentation, due to the limitation of the number of inter-chip pins, as the number of cores increases, the number of FPGA inter-chip connections increases sharply, and this ...

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Problems solved by technology

[0005] When performing FPGA simulation verification, after FPGA fragmentation, due to the limitation of the number of inter-chip pins, as the number of cores increases, the number of FPGA inter-chip connections increases sharply, and this kind of one-to-many maintenance cannot be realized on a multi-core scale star topology

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