Substrate-free system-in-package structure and method and electronic product
A system-level packaging, electronic product technology, applied in circuits, electrical components, electrical solid devices, etc., can solve the problem of large chip packaging, improve product production efficiency and product quality, and reduce poor product quality.
Inactive Publication Date: 2020-09-29
GREAT TEAM BACKEND FOUNDRY (DONGGUAN) LTD
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Problems solved by technology
This packaging method requires a large volume of plastic packaging layer, resulting in excessive chip packaging volume
Method used
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[0028] In order to make the technical problems solved by the present invention, the technical solutions adopted and the technical effects achieved clearer, the technical solutions of the embodiments of the present invention will be further described in detail below. Obviously, the described embodiments are only part of the embodiments of the present invention. rather than all examples. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts fall within the protection scope of the present invention.
[0029] In the description of the present invention, unless otherwise clearly stipulated and limited, the terms "connected", "connected" and "fixed" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral body; It can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an ...
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The embodiment of the invention discloses a substrate-free system-in-package structure, a substrate-free system-in-package method and an electronic product. According to the technical scheme providedby the embodiment of the invention, a pin of a first chip is led out through a rewiring layer, the first chip and a passive element are packaged through a first packaging layer, a pin of a second chippenetrates through the first chip and is connected with the rewiring layer, therefore, pins of the second chip are led out to the rewiring layer, the second chip is packaged through the second packaging layer, tin soldering bumps on the rewiring layer can be electrically connected with the outside, the situation that the size of the packaging layer is too large due to connection of the bonding metal wires is reduced, a problem that the packaging structure is too large in size due to the fact that the bonding wire bonding process is not stable is effectively solved, a problem of poor product quality caused by instability of the bonding wire bonding process is effectively reduced, product production efficiency and the product quality are improved, and meanwhile, an added passive element canenable the product to have more functions.
Description
technical field [0001] The embodiments of the present application relate to the technical field of semiconductor packaging, and in particular to a substrateless system-in-package structure, method, and electronic product. Background technique [0002] A semiconductor is a material whose conductivity is between that of a conductor and a non-conductor. According to the characteristics of semiconductor materials, a semiconductor element is a solid-state element. Its volume can be reduced to a small size, so it consumes less power and has a high degree of integration. The field of electronic technology has been widely used. [0003] In the existing chip stack packaging scheme, the first chip and the second chip are generally packaged in a plastic packaging layer, the second chip is placed above the first chip, and a conductive plug is arranged in the plastic packaging layer, and the bottom end of the conductive plug is electrically connected. The pins of the first chip are conn...
Claims
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IPC IPC(8): H01L23/31H01L23/498H01L25/16H01L21/56H01L21/60
CPCH01L21/56H01L23/3114H01L23/49816H01L23/49827H01L24/85H01L25/16H01L2224/85986H01L2224/16225H01L2924/181H01L2924/00012
Inventor 王琇如
Owner GREAT TEAM BACKEND FOUNDRY (DONGGUAN) LTD