Substrate-free chip stacking and packaging structure and method and electronic product
A technology of chip stacking and packaging structure, which is applied in the direction of circuits, electrical components, electric solid devices, etc., can solve the problems of large chip packaging volume, improve product production efficiency and product quality, and reduce product quality.
Inactive Publication Date: 2020-09-29
GREAT TEAM BACKEND FOUNDRY (DONGGUAN) LTD
View PDF5 Cites 0 Cited by
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
This packaging method requires a large volume of plastic packaging layer, resulting in excessive chip packaging volume
Method used
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View moreImage
Smart Image Click on the blue labels to locate them in the text.
Smart ImageViewing Examples
Examples
Experimental program
Comparison scheme
Effect test
Embodiment Construction
[0031] In order to make the technical problems solved by the present invention, the technical solutions adopted and the technical effects achieved clearer, the technical solutions of the embodiments of the present invention will be further described in detail below. Obviously, the described embodiments are only part of the embodiments of the present invention. rather than all examples. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts fall within the protection scope of the present invention.
[0032] In the description of the present invention, unless otherwise clearly stipulated and limited, the terms "connected", "connected" and "fixed" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral body; It can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an ...
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More PUM
Login to View More Abstract
The embodiment of the invention discloses a substrate-free chip stacking and packaging structure and method and an electronic product. The method is characterized in that a pin of a first chip is ledout through a rewiring layer, the first chip is packaged through a first packaging layer, a metal connecting column electrically connected with the rewiring layer is arranged at the first packaging layer, a pin of a second chip is electrically connected with the metal connecting column, therefore, pins of the second chip are led out to the rewiring layer, the second chip is packaged through the second packaging layer, tin soldering bumps on the rewiring layer can be electrically connected with the outside, therefore, a problem that the size of the packaging structure is too large due to the fact that the size of the packaging layer is too large due to connection of the bonding metal wires is solved, a problem that the product quality is poor due to instability of the routing process of thebonding metal wires is effectively solved, and product production efficiency and the product quality are improved.
Description
technical field [0001] The embodiments of the present application relate to the technical field of semiconductor packaging, and in particular to a substrateless chip stack packaging structure, method and electronic product. Background technique [0002] A semiconductor is a material whose conductivity is between that of a conductor and a non-conductor. According to the characteristics of semiconductor materials, a semiconductor element is a solid-state element. Its volume can be reduced to a small size, so it consumes less power and has a high degree of integration. The field of electronic technology has been widely used. [0003] In the existing chip stack packaging scheme, the first chip and the second chip are generally packaged in a plastic packaging layer, the second chip is placed above the first chip, and a conductive plug is arranged in the plastic packaging layer, and the bottom end of the conductive plug is electrically connected. The pins of the first chip are co...
Claims
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More Application Information
Patent Timeline
Login to View More Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/498H01L23/31H01L25/00H01L21/56H01L21/60
CPCH01L21/56H01L23/3114H01L23/49816H01L23/49838H01L24/85H01L25/00H01L2224/85986H01L2224/16225H01L2224/18
Inventor 王琇如
Owner GREAT TEAM BACKEND FOUNDRY (DONGGUAN) LTD