Power-on reset circuit capable of preventing power supply jitter

Abstract

A power-on reset circuit capable of preventing power supply jitter relates to the technology of integrated circuits and comprises a power-on trigger circuit, a third PMOS transistor, an anti-interference delay circuit and a counter circuit, the anti-interference delay circuit comprises an NAND gate, the output end of the NAND gate is connected with the grid electrode of the third PMOS transistor,the first input end of the NAND gate is connected with a second reference point B, the second input end of the NAND gate is connected with the second reference point B through X inverters connected inseries, and X is an even number larger than 1; the output end of the NAND gate is connected with the EN end of the counter through an inverter, the output end of the counter serves as the output endof a power-on reset circuit and is connected to one input end of one NOR gate, the other input end of the NOR gate is connected with the oscillator, and the output end of the NOR gate is connected with the counting pulse input end of the counter. The reset time of the internal circuit is ensured, and the reliability of the circuit is improved.

Description

technical field [0001] The present invention relates to integrated circuit technology. Background technique [0002] As we all know, in the design of large-scale digital-analog mixed-signal integrated circuit chips, due to the existence of a large number of digital units such as control registers, status registers, and counters in the chip, when the system is just connected to the power supply and the power supply is in the rising stage, the Status is indeterminate. These uncertain states may cause misoperation of the chip and affect the reliability and stability of the chip. Therefore, a circuit is required to provide a global reset signal for the chip during the power-on process of the system to reset the initial state of the entire chip. Assign a value to ensure that the chip can start from a certain state. This circuit is a power-on reset circuit (Power on Reset, POR for short). [0003] Traditional POR circuits such as figure 1 As shown, it includes a reference volta...

AI Technical Summary

Problems solved by technology

When the power supply voltage Vdd rises, the voltage at point A is the value of Vdd divided by R1 and R2, so the voltage at point A rises as Vdd rises. When the voltage at point A rises to the output voltage of vref, the output POR of the comparator Comp changes from low If Vdd has other interference during the rising phase, such as noise, crosstalk from the board level, etc., the voltage at point A of its divided voltage will jitter around the vref voltage. After passing through the comparator, it will be Unexpected reset pulses will be generated at the reset terminal, which will cause disorder in the internal circuit of the chip and output wrong data

[0004] At present, the industry has come up with many solutions to improve the POR anti-interference ability. Although these solutions can achieve certain effects, the disadvantage is that the circuit structure is relatively complicated, and circuits such as operational amplifiers are often required, which consumes a lot of power and is still expensive. Pole-zero and start-up circuits need to be considered

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