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Prefetcher based speculative dynamic random-access memory read request technique

A technology for reading requests and memory, applied in memory systems, instruments, climate sustainability, etc., and can solve problems affecting system performance, etc.

Active Publication Date: 2020-10-27
ADVANCED MICRO DEVICES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Servicing a miss from the last level cache (e.g., L3 cache 112) by accessing main memory 114 has high memory access latency (e.g., memory access latency of at least 200 clock cycles), which can significantly affect system performance

Method used

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  • Prefetcher based speculative dynamic random-access memory read request technique
  • Prefetcher based speculative dynamic random-access memory read request technique
  • Prefetcher based speculative dynamic random-access memory read request technique

Examples

Experimental program
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Embodiment Construction

[0016] One technique for reducing the miss latency of a last level cache (eg, L3 cache) includes issuing speculative DRAM read requests (ie, speculative memory read requests). The technique speculatively issues DRAM read requests to main memory before read requests are actually needed to reduce average last level cache miss latencies. Although speculative DRAM read requests increase the instructions per cycle of the system, while executing, conventional speculative DRAM read requests can adversely affect system performance by increasing congestion at the main memory interface. Therefore, conventional speculative DRAM read requests may increase rather than decrease memory system latency. As the number of execution threads in the system increases, shared last level cache misses increase due to increased contention, thereby increasing memory system access latencies.

[0017] figure 2 and image 3 Multi-core processing system 200 is shown including a cluster of processors: pro...

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Abstract

A method includes monitoring a request rate of speculative memory read requests from a penultimate-level cache to a main memory. The speculative memory read requests correspond to data read requests that missed in the penultimate-level cache. A hit rate of searches of a last-level cache for data requested by the data read requests is monitored. Core demand speculative memory read requests to the main memory are selectively enabled in parallel with searching of the last-level cache for data of a corresponding core demand data read request based on the request rate and the hit rate. Prefetch speculative memory read requests to the main memory are selectively enabled in parallel with searching of the last-level cache for data of a corresponding prefetch data read request based on the requestrate and the hit rate.

Description

Background technique [0001] Typically, to bridge the gap between processor core speed and main memory speed, processor systems use a multi-level cache hierarchy, where each cache is larger than its predecessor and faster than its successor. figure 1 An exemplary processing system is shown that includes a multi-level cache hierarchy with three cache levels and main memory. Processing system 100 includes processor 102 having a split L1 cache (eg, instruction cache 106 and data cache 108 ) coupled to L2 cache 110 . Level 3 cache 112 is external to processor 102 and communicates with main memory 114, which may include conventional off-chip dynamic random access memory (DRAM), faster on-chip DRAM, and / or include memory technologies such as DRAM, static random access memory (SRAM), phase change memory, memristor, or a mix of other memory types). Servicing a miss from the last level cache (e.g., L3 cache 112) by accessing main memory 114 has high memory access latency (e.g., memory...

Claims

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Application Information

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IPC IPC(8): G06F12/0862G06F12/0811G06F11/30G06F3/06
CPCG06F12/0811G06F12/0862G06F12/084G06F12/0842G06F12/0846G06F12/0859G06F2212/1024G06F2212/502Y02D10/00G06F11/3037G06F3/0656G06F3/0611G06F3/0653G06F2212/602G06F12/0897G06F3/0683
Inventor 塔努吉·库马尔·阿加瓦尔阿纳苏阿·霍米克道格拉斯·班森·亨特
Owner ADVANCED MICRO DEVICES INC