[0048] In order to enable those skilled in the technical field to better understand the technical scheme of the present invention, the present invention will be further explained in detail with reference to the accompanying drawings.
[0049] It should be noted that "the first" and "the second" in the present invention only represent different parts, and there is no order to Figure 6 For example, the vertical paper is left to left, the vertical paper is right to right, the vertical paper is up, and the vertical paper is down. The laser 102 is a single-mode DFB laser, the modulator 103 is a photoelectric absorption modulator, and the detector 105 is a photodetector.
[0050] In this embodiment, for example Figure 5 、 Figure 6 As shown, the SOI substrate 101 includes a silicon substrate layer 1, a silicon dioxide insulating layer 10, a silicon waveguide layer 11, and a silicon dioxide protective layer 12 which are sequentially stacked from bottom to top.
[0051] The silicon-based III-V quantum dot photon transceiver module integrates a single-mode DFB laser, a photoelectric absorption modulator and a photodetector which are sequentially arranged on the silicon substrate layer of the SOI substrate 101 from left to right, and a silicon waveguide 104 arranged between the photoelectric absorption modulator and the photodetector, wherein:
[0052] The DFB laser generates stable single-mode laser by DC driving current, and then transmits the light to the photoelectric absorption modulator in the same ridge waveguide.
[0053]The photoelectric modulator uses reverse bias to load the high-speed electrical signal on the light wave generated by the single-mode DFB laser, and conducts the modulated high-speed optical signal to the silicon waveguide 104 for signal transmission;
[0054] The silicon waveguide 104 transmits optical signals to other silicon optical passive devices;
[0055] The photodetector receives the high-frequency optical signal transmitted by the silicon waveguide 104 and converts the received high-frequency optical signal into an electrical signal.
[0056] Figure 1 A flowchart of the method of monolithic integration of photonic devices based on silicon quantum dots proposed by the present invention is shown. The method comprises the following steps:
[0057] S1, firstly, a graphic window is prepared on a preset active module area of an SOI substrate 101, and the graphic window area is etched to a silicon substrate layer 1 to obtain epitaxial windows 201 of a laser 102, a modulator 103 and a detector 105;
[0058] S2, selectively growing epitaxial structure layers of III-V quantum dots in the epitaxial window 201 by MBE equipment, and then performing selective area annealing treatment on the epitaxial structure layers of the laser 102 and the modulator 103 to make the energy band gaps of the active areas of the laser 102 and the modulator 103 different;
[0059] S3, etching the silicon waveguide 104;
[0060] S4, ridge waveguide etching is performed on the epitaxial structure layers of the laser 102, the modulator 103 and the detector 105, then the side grating etching is performed on the ridge waveguide of the laser 102, and the ridge waveguide of the laser 102 and the modulator 103 is electrically isolated and etched at the same time;
[0061] S5, plating the protective layer and insulating layer on the ridge waveguides of the laser 102, the modulator 103 and the detector 105, patterning the protective layer and the insulating layer, windowing the top layer, and then flattening;
[0062] S6, evaporating the positive electrode 13 and the negative electrode on the laser 102, the modulator 103 and the detector 105, and performing RTP(Rapid Thermal Processing) processing;
[0063] S7, thinning and cutting are carried out in the later stage.
[0064] In this embodiment, the quantum dot laser 102 and other active and passive optoelectronic devices are monolithically integrated on the CMOS compatible SOI substrate 101 by using the high-quality III-V direct epitaxy technology on silicon and quantum dot technology, giving full play to the advantages of silicon-based photonics, so as to obtain a silicon-based quantum dot optical transceiver module integrated with the laser 102, modulator 103, silicon waveguide 104 and detector 105. The modulator 103 and the silicon waveguide 104 and the detector 105 and the silicon waveguide 104 are in butt coupling mode, so the silicon waveguide layer 11 is at the same height as the center of the active area of 5-7 periods of high-density quantum dots.
[0065] In this embodiment, the specific implementation of step S1 is as follows: firstly, a pattern window is prepared on the preset active module area of SOI substrate 101 by photolithography technology, and then epitaxial windows 201 of laser 102, modulator 103 and detector 105 are etched on the prepared pattern window area by RIE(Reactive-ion etching) technology or ICP (Inductively Coupled Ion Etching) technology, so that SOI substrate 105 can be made of silicon dioxide.
[0066] Figure 2 The flow chart of the method of selectively growing epitaxial structure layer of III-V quantum dots in epitaxial window and selectively annealing in the present invention is shown. Figure 6 The front view of the silicon-based III-V quantum dot photon transceiver module of the present invention. The method comprises the following steps:
[0067] S21, firstly, a silicon epitaxial layer is grown on the silicon substrate layer 1 in the epitaxial window 201 by MBE(Molecular beam epitaxy) equipment, then a III-V group heterostructure is grown on the silicon epitaxial layer, and the III-V group quantum dot epitaxial structure layer is obtained by combining the high-temperature annealing technology;
[0068] S22, a silicon dioxide capping layer with a thickness of 150-300nm is prepared by PECVD (plasma enhanced chemical vapor deposition) and pattern etching on the surface of the epitaxial structure layer of the modulator 103, and the preparation temperature is 300-350℃.
[0069] S23, using PVD(Physical Vapor Deposition) to prepare a titanium dioxide capping layer with a thickness of 150-300nm on the epitaxial structure layer of the laser 102, and the preparation temperature is 30-100.degree. C.;
[0070] S24, standing at 700-750℃ for 15-60s for rapid quenching, and then putting in hydrofluoric acid to wash off the silica cover layer and titanium dioxide cover layer.
[0071] In this embodiment, since the epitaxial window 201 etched in the pattern window area of the active module (laser 102, modulator 103 and detector 105) is often not smooth, in order to improve the yield, a thin silicon epitaxial layer needs to be grown on the silicon substrate layer 1 of the epitaxial window 201 to smooth the surface of the silicon substrate layer 1 before growing the III-V materials, and this can also bury the impurities generated in the etching process to a certain extent. Then, combined with high-temperature annealing technology and III-V group materials, a nodule layer and a superlattice dislocation filter layer are prepared on the silicon epitaxial layer, so that defects such as APDs (reverse domains) and TDs (threading dislocations) can be effectively suppressed, and a high-quality silicon-based III-V group quantum dot epitaxial structure layer can be obtained, such as Figure 6 As shown, the silicon-based III-V quantum dot epitaxial structure layer includes III-V buffer layer 2, N-type contact layer 3, N-type light confinement layer 4, 5-7 periodic high-density quantum dot active areas, P-type light confinement layer and P-type contact layer 7 which are sequentially stacked from bottom to top, wherein:
[0072] The thickness of the III-V buffer layer 2 is 1-1.5μm, and it is made of gallium arsenic material.
[0073] The thickness of the N-type contact layer 3 is 300-400nm, and it is made of gallium-arsenic material doped with silicon at a concentration of 1×10. 18 cm -3 -3×10 18 cm -3;
[0074] The thickness of the N-type light confinement layer 4 is 1.3-1.5μm, and it is made of silicon-doped Al-Ga-As material with a concentration of 1×10. 18 cm -3 -3×10 18 cm -3;
[0075]5-7 periods of high-density quantum dot active areas are indium-arsenic quantum dot active areas, and the growth steps of each period are as follows: firstly, grow a gallium-arsenic infiltration layer with a thickness of 30-70nm, then deposit an indium-arsenic quantum dot material layer with a thickness of 2-4, then deposit an indium-gallium-arsenic covering layer with a thickness of 5-10nm on the indium-arsenic quantum dot material layer, and finally grow a gallium-arsenic spacer layer with a thickness of 50-70nm. In this embodiment, since the laser 102 and the detector 105 can be the same quantum dot heterostructure, and the energy band gap required by the active area of the modulator 103 should be slightly larger than that required by the active areas of the laser 102 and the detector 105 to meet the modulation requirements of low loss and high modulation depth, The 5-7 period high-density quantum dot active areas include the first 5-7 period high-density quantum dot active areas 5 (thickness 1300nm) located in the active areas of laser 102 and detector 105, and the second 5-7 period high-density quantum dot active areas 8 (thickness 1260nm) located in the active areas of modulator 103, and the second 5-7 period high-density quantum dot active areas 8 of modulator 103 need to use selective areas. Moreover, due to the different thermal expansion coefficients of silicon dioxide and titanium dioxide, the quantum dots covered by the silicon dioxide will have different degrees of intermixing effect. Specifically, the thermal expansion coefficient of the silicon dioxide cover layer is much smaller than that of the gallium arsenide layer under the silicon dioxide cover layer, resulting in compressive stress, which promotes the intermixing phenomenon of quantum dots and makes the band gap of the covered area blue shift. On the contrary, the thermal expansion coefficient of the titanium dioxide cover layer is much larger than that of the gallium arsenide layer under it, and the tensile force generated by the titanium dioxide cover layer will inhibit the quantum dots from mixing, and the energy band gap of the covered area will basically remain unchanged, thus realizing the difference of the energy band gap between the quantum dots in the active area of the laser 102 and the active area of the modulator 103, and thus meeting the requirements of multifunctional integrated circuits.
[0076] The thickness of the P-type optical confinement layer is 1.3-1.5μm, and it is made of Al-Ga-As material doped with Beryllium, and the concentration of Beryllium is 5×10. 17 cm -3 -9×10 17 cm -3. In this embodiment, the p-type optical confinement layer includes a first p-type optical confinement layer 6 and a second p-type optical confinement layer 9, the first p-type optical confinement layer 6 is located between the first 5-7 period high-density quantum dot active area 5 and the p-type contact layer 7 in the active area of the modulator 103 and the detector 105, and the second p-type optical confinement layer 9 is located between the second 5-7 period high-density quantum dot active area 8 and the p-type contact layer 7 in the active area of the laser 102. Among them, the second p-type optical confinement layer 9 located in the active region of the laser 102 is a DFB side grating, but in its embodiment, a simple multi-wavelength Perot (FP) laser can also be used. Compared with DFB grating, its manufacturing process is more simplified, which can further reduce the cost. Although the multi-wavelength Perot (FP) laser is not suitable for long-distance transmission, it is widely used in medium and short-distance transmission, such as in data center or local area network (LAN). Therefore, for different use scenarios, the laser type of the laser 102 can be adjusted according to the actual situation to achieve the maximum cost-effectiveness. In this embodiment, the material of the area of the first p-type light confinement layer 6 and the area of the second p-type light confinement layer 9 are completely the same, and the only difference is that the area of the first p-type light confinement layer 6 has no grating etching, while the area of the second p-type light confinement layer 9 has etched grating.
[0077] The p-type contact layer 7 is a highly doped p-type gallium arsenic contact layer with a thickness of 300-400nm and a doping concentration of 1×10. 19 cm -3 -3×10 19 cm -3.
[0078] The specific implementation of the step S3 is to etch the silicon waveguide 104 by using the RIE technology or ICP technology, and the width of the etched waveguide is 1-3 μ m. In this embodiment, because the waveguide width is determined by the light spot emitted by the laser 102, the etched waveguide width is selected to be between 1 and 3 μ m. In addition, the end quality of the modulator 103, the end quality of the silicon waveguide 104 and the distance from the end of the modulator 103 to the end of the silicon waveguide 104 (i.e., the width of the groove 202) are the main factors that affect the normal operation of the integrated device. Therefore, the end surfaces of the modulator 103 and the silicon waveguide 104 are smooth.
[0079] Figure 3 There is shown a flow chart of the method for etching the ridge waveguide of the epitaxial structure layer and etching the side grating and electrical isolation of the ridge waveguide in the present invention. The method includes the following steps:
[0080] S41: firstly, the epitaxial layers of the laser 102, the modulator 103 and the detector 105 are etched with ridge waveguide by photolithography and ICP technology. The etching depth is 3.4-3.7μm to expose the N-type contact layer 3, and the etching width is 2-5μm to ensure the single longitudinal mode (TME) of the laser 102 00 ) the generation of light spots;
[0081] S42, etching the ridge waveguide of the laser 102 with different grating periods on its side by photolithography and ICP technology;
[0082] S43. Finally, the ridge waveguide of the laser 102 and the modulator 103 is electrically isolated and etched to disconnect the P-type contact layer 7 between the laser 102 and the modulator 103.
[0083] In this embodiment, firstly, the epitaxial layers of the laser 102, the modulator 103 and the detector 105 are etched with ridge waveguides to expose the N-type contact layer 3 in the corresponding areas. In order to ensure the low-loss transmission of optical signals, the ridge waveguides etched on the epitaxial layers of the laser 102, the modulator 103 and the detector 105 are on the same line as the silicon waveguide 104. Then, the ridge waveguide of laser 102 is etched with different grating periods on its side by photolithography and ICP technology, in which the grating period is designed to correspond to the wavelength of laser 102. In order to ensure the generation of single transverse mode laser, we design λ/4 phase offset in the middle of DFB laser. By etching different grating periods, single-mode DFB lasers with different single wavelengths can form an array, thus achieving multi-channel signal transmission. Finally, the ridge waveguide of DFB laser and modulator 103 is electrically isolated and etched with an etching depth of 300-400nm to ensure that the P-type contact layer 7 between DFB laser and modulator 103 is in a disconnected state.
[0084] Figure 4 The flow chart of the method of plating protective layer and insulating layer on ridge waveguide of active device and subsequent treatment in the present invention is shown. The method comprises the following steps:
[0085] S51: firstly, the ridge waveguides of the laser 102, the modulator 103 and the detector 105 are plated with a layer of Al2O3 with a thickness of 10-20nm as a protective layer by PVD, and then a layer of SiO2 or NO2 with a thickness of 200-500nm is plated on the protective layer by PECVD as an insulating layer;
[0086] S52, patterning the protective layer and insulating layer in step S51 and windowing the top layer to expose the P-type contact layer 7 of the ridge waveguide of the laser 102, the modulator 103 and the detector 105;
[0087] S53. Finally, spin coating and planarization etching of planarization materials are carried out to ensure that there is no material residue on the ridge waveguide.
[0088] In this embodiment, firstly, the protective layer and insulating layer are coated on the ridge waveguides of laser 102, modulator 103 and detector 105 by PVD and PECVD in sequence, then the protective layer and insulating layer are patterned and the top layer is windowed to expose the P-type contact layer 7 of the ridge waveguide, and finally, the planarization material spin coating and planarization etching are performed to ensure that there is no material residue on the ridge waveguides of laser 102, modulator 103 and detector 105.
[0089] Among them, the positive electrode 13 on the P-type contact layer 7 is deposited by photolithography, electron beam sputtering or magnetron sputtering on the P-type contact layer 7 of the ridge waveguide of the laser 102, modulator 103 and detector 105, and then RTP treatment is performed to form ohmic contact with low resistance.
[0090] And finally, post-processing the silicon-based III-V quantum dot photon transceiver module. In this embodiment, firstly, the SOI silicon substrate 101 is thinned to a thickness of 200-120μm by a grinder, which on the one hand can reduce the influence of thermal effect on integrated devices, and on the other hand, the thinned SOI silicon substrate 101 is also beneficial to the subsequent cutting process. Then, the thinned SOI silicon substrate 101 is cut to obtain the treated silicon-based III-V quantum dot photon transceiver module.
[0091] It should be noted that the large-size SOI silicon substrate 101 of the present invention can be manufactured in large quantities at one time, so this technology is suitable for low-cost commercial applications.
[0092] The above method of monolithic integration of photonic devices based on silicon quantum dots provided by the invention is introduced in detail. In this paper, specific examples are used to explain the principle and implementation of the present invention, and the explanations of the above embodiments are only used to help understand the core idea of the present invention. It should be pointed out that for those of ordinary skill in the technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.
