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Method for performing sudden power off recovery management, memory device, controller, and electronic device

A memory device and controller technology, applied in the field of flash memory access, can solve problems such as long boot time or boot failure, and achieve the effect of optimizing performance

Pending Publication Date: 2020-11-24
SILICON MOTION INC (CN)
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For example, since the capacity of the flash memory increases with certain specification changes, the management mechanism of these memory devices for Sudden Power Off (SPO) events requires more time to perform related operations, which may cause a lot of damage. Long boot time or boot failure

Method used

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  • Method for performing sudden power off recovery management, memory device, controller, and electronic device
  • Method for performing sudden power off recovery management, memory device, controller, and electronic device
  • Method for performing sudden power off recovery management, memory device, controller, and electronic device

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Embodiment Construction

[0056] figure 1 It is a schematic diagram of an electronic device 10 according to a first embodiment of the present invention, wherein the electronic device 10 may include a host device (host device) 50 and a memory device 100, and the memory device 100 may be used to store information for the host device 50 . According to this embodiment, the memory device 100 can be used to provide storage space for the host device 50, and can obtain one or more driving voltages from the host device 50 as the power source of the memory device 100, but the invention is not limited thereto. The main device 50 may include: at least one processor (such as one or more processors), which may be generally referred to as a processor 52, and related circuits such as random access memory (Random Access Memory, RAM), bus, etc.; and a power supply A supply circuit 54 , wherein the processor 52 and the power supply circuit 54 are coupled to each other. The processor 52 can be used to control the operat...

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PUM

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Abstract

A method for performing sudden power off recovery management, a memory device, a controller, and an electronic device are disclosed. The method may include: triggering writing an expansion block; regarding a target block, setting a page count and a start page number for being processed with binary search; at least according to the page count and the start page number, performing the binary searchon the target block to find a first empty page within the target block; performing page-by-page search, starting from the first empty page in a backward direction within the target block, to find thelast valid page within the target block; determining an abandonment range within the expansion block according to the last valid page and the first empty page; and performing dummy programming on allexpansion pages within the abandonment range. When a power-off event occurs, the operation of the system is quickly recovered through a high-performance power-off recovery mechanism in the controller.

Description

technical field [0001] The present invention relates to the access of flash memory (Flash memory), especially a method for managing without warning power-off recovery (Sudden Power Off Recovery, SPOR), related memory devices and their controllers, and related electronic device. Background technique [0002] Flash memory can be widely used in various portable or non-portable memory devices (for example: memory cards conforming to SD / MMC, CF, MS, XD or UFS standards; another example: solid state hard drives; another example: conforming to UFS or EMMC standard embedded (embedded) storage device). In terms of commonly used NAND flash memory, there are initially single level cell (single level cell, SLC) and multiple level cell (multiple level cell, MLC) flash memories. Due to the continuous development of memory technology, newer memory device products may use triple level cell (TLC) flash memory, or even quadruple level cell (QLC) flash memory. In order to ensure that the ac...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/14G06F12/02
CPCG06F11/1441G06F11/1469G06F12/0246G06F3/0679G06F3/064G06F3/0619G06F3/0616G06F1/30G06F3/0659G06F3/0604
Inventor 谢松晏
Owner SILICON MOTION INC (CN)
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