Hardware analysis method for Binary protocol data stream
A parsing method and data stream technology, applied in the parsing field of Binary protocol data stream, can solve problems such as large delay and resource occupation, and achieve the effect of reducing processing delay, improving processing capacity, and improving decoding efficiency
Active Publication Date: 2020-12-25
山东产研集成电路产业研究院有限公司
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Problems solved by technology
These transaction data are formatted through the Binary protocol (Binary protocol to format the business demand process, making it a functional process that can be described in computer language, and uniformly exchange the format on each business function interface. Refer to the engineering technical standard "Shenzhen Securities Exchange The Binary transaction data interface specification (Ver1.13)") is transmitted and further processed by the computer. Due to the huge amount of transaction data, it will cause serious resource occupation and large delays.
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[0024] The hardware that can be selected in this embodiment is FPGA or special-purpose AISC, preferably FPGA in this embodiment, FPGA device belongs to a kind of semi-custom circuit in application-specific integrated circuit, is a programmable logic array. During implementation, the corresponding execution program is downloaded into the FPGA, and the FPGA is configured to have an input interface buffer, a decoding module and an output interface buffer, and the input interface buffer is used to store the original Binary protocol data stream received, the said The decoding module is used to perform field matching on the data stream according to the Binary protocol, and the output interface cache is used to cache the matched fields.
[0025] Such as figure 2 As shown, the input interface cache adopts the standard AXI-Stream interface FIFO memory, which has fast data speed and strong external portability, and can be directly connected to existing PCI-E devices or Ethernet devices...
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The invention relates to a hardware analysis method for a Binary protocol data stream, which comprises the following steps of: downloading a decoding program into an FPGA (Field Programmable Gate Array) or solidifying the decoding program into an ASIC (Application Specific Integrated Circuit) (needing tape-out), sending out a transaction data stream by a deep exchange server, inputting the transaction data stream into the FPGA or the ASIC through a network interface or a PCIE (Peripheral Component Interconnect Express) interface, and caching in an input interface; adjusting the length of eachdata packet by a packet reforming module, then entering a decoding module, and enabling the decoding module to strip and decode data according to the steps to obtain decoded data, send the decoded data to an output interface cache, and outputs the decoded data to a client CPU through the network interface or aPCIE interface to obtain the decoded data. Through special hardware decoding, the decoding speed is greatly improved, the burden of a computer can be reduced, and great economic benefits are achieved.
Description
technical field [0001] The invention relates to an analysis method of Binary protocol data flow, in particular to a hardware analysis method. Background technique [0002] With the development of my country's economy, the securities industry has made great progress. Shenzhen Stock Exchange (hereinafter referred to as "Shenzhen Stock Exchange"), as one of the main trading places in my country, generates a large amount of transaction data every day. These transaction data are formatted through the Binary protocol (Binary protocol to format the business demand process, making it a functional process that can be described in computer language, and uniformly exchange the format on each business function interface. Refer to the engineering technical standard "Shenzhen Securities Exchange The Binary transaction data interface specification (Ver1.13)") is transmitted and further processed by the computer. Due to the huge amount of transaction data, it will cause serious resource occ...
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Login to View More IPC IPC(8): G06F13/40H04L29/06
CPCG06F13/4068G06F13/4009H04L69/06H04L69/22
Inventor 滕达温士魁
Owner 山东产研集成电路产业研究院有限公司