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Integrated circuit die

A technology of integrated circuits and chips, applied in circuits, electrical components, electrical solid-state devices, etc., to solve problems such as short circuits and memory cells not working properly

Inactive Publication Date: 2020-12-29
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This redeposition of material from the top electrode can lead to a short circuit between the first and second magnetic plates of the magnetic tunnel junction
If there is a short circuit between the first magnetic plate and the second magnetic plate at the magnetic tunnel junction, the memory cell will not work properly

Method used

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  • Integrated circuit die
  • Integrated circuit die
  • Integrated circuit die

Examples

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Embodiment Construction

[0046] In the following description, various thicknesses and materials are described for various layers and structures within an integrated circuit wafer. Specific dimensions and materials of various embodiments are given by way of example. Those skilled in the art will recognize that, in light of the present disclosure, other dimensions and materials may in many cases be used without departing from the scope of the present disclosure.

[0047] The following disclosure provides a number of different embodiments, or examples, for implementing different features of the described subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are examples only and are not intended to be limiting. For example, in the following description, a first feature formed over or on a second feature may include embodiments in which the first feature is formed in direct contact with the second feature, and may also i...

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Abstract

An integrated circuit die includes a magnetic tunnel junction as a storage element of a MRAM cell. The integrated circuit die includes a top electrode positioned on the magnetic tunnel junction. The integrated circuit die includes a first sidewall spacer laterally surrounding the top electrode. The first sidewall spacer acts as a mask for patterning the magnetic tunnel junction. The integrated circuit die includes a second sidewalls spacer positioned on a lateral surface of the magnetic tunnel junction.

Description

technical field [0001] This disclosure is in the field of integrated circuits. More particularly, the present disclosure relates to integrated circuits including magnetic random access memory (MRAM) cells. Background technique [0002] An MRAM cell includes a magnetic data storage element. In general, an MRAM cell includes a magnetic tunnel junction as a data storage device. The magnetic tunnel junction includes a first magnetic plate and a second magnetic plate separated by a thin barrier layer. The first magnetic plate is a permanent magnet with a fixed magnetization direction. The second magnetic slab has a magnetization direction that can be selectively changed by passing a current adjacent to the second magnetic slab. The electrical resistance between the two magnetic plates is based in part on the alignment of the magnetization directions of the first and second plates. Therefore, data is written into the MRAM cell by adjusting the magnetization direction of the s...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L43/08H01L27/22H10N50/10H10N50/80H10N50/01
CPCH10B61/00H10N50/10H10N50/85H10N50/01H10N50/80
Inventor 庄学理陈俊尧王宏烵
Owner TAIWAN SEMICON MFG CO LTD