Manufacturing method of three-dimensional memory and three-dimensional memory

Abstract

The present invention provides a method for manufacturing a three-dimensional memory and a three-dimensional memory. In the method for manufacturing a three-dimensional memory, a plurality of first dummy metal contact structures are formed around the first metal contact structure in an array chip, so that subsequent The static electricity caused by etching is shared and drained; in addition, in the circuit chip, a static elimination circuit electrically connected with the first dummy metal contact structure is added, so that the static electricity elimination circuit can capture or eliminate the static electricity accumulated on the first dummy metal contact structure. Static electricity, further strengthen the sharing and drainage effect of static electricity, so that the amount of static electricity transmitted to the control circuit on the circuit chip through the first metal contact structure and the second metal contact structure can be greatly reduced, and the static electricity caused by etching can be effectively avoided. The damage of the circuit chip enhances the structural stability and reliability of the control circuit on the circuit chip.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a three-dimensional memory and a three-dimensional memory. Background technique [0002] Three-dimensional memory is a technology for stacking data units. At present, data units of 32 layers and above can be stacked. It overcomes the limitation of the actual expansion limit of planar memory, further increases the storage capacity, and reduces the storage cost of each data bit. , reducing energy consumption. [0003] However, in the current manufacturing method of three-dimensional memory, after the array chip and the circuit chip are bonded, it is necessary to etch the substrate of the array chip to extract the metal interconnection structure from the back of the array chip, which requires the use of plasma Etching and deposition processes, among which, plasma etched ions carry a lot of static electricity, which will be transmitted t...

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Problems solved by technology

[0003] However, in the current manufacturing method of three-dimensional memory, after the array chip and the circuit chip are bonded, it is necessary to etch the substrate of the array chip to extract the metal interconnection structure from the back of the array chip, which requires the use of plasma Etching and deposition processes, among which, plasma etched ions carry a lot of static electricity, which will be transmitted to each control circuit in the circuit chip along the metal interconnection structure, causing damage to the structure of the control circuit, resulting in three-dimensional memory drop in reliability

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