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A kind of anti-single event effect finfet device and preparation method

An anti-single event effect and device technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of short current channel, large parasitic transistor gain, serious single event effect, etc., and achieve long current channel. , reduce the gain, avoid the effect of the single event effect

Active Publication Date: 2021-11-02
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The STI thickness between planar process transistors with the same feature size is about 2 to 3 times the STI thickness between FinFET process transistors. The current channel of the single event effect of FinFET is shorter, and the gain of parasitic transistors is greater, which makes the single event effect of FinFET strain seriously

Method used

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  • A kind of anti-single event effect finfet device and preparation method
  • A kind of anti-single event effect finfet device and preparation method
  • A kind of anti-single event effect finfet device and preparation method

Examples

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Effect test

Embodiment 1

[0050] See figure 1 with figure 2 , figure 1 It is a schematic flow chart of a method for preparing a FinFET device resistant to single event effects provided by an embodiment of the present invention, figure 2 It is a schematic diagram of the preparation process of a method for preparing a FinFET device resistant to single event effects provided by an embodiment of the present invention. This embodiment provides a method for manufacturing a FinFET device resistant to single event effects, and the method for manufacturing the FinFET device includes:

[0051] Step 1, preparing a substrate layer 1 doped with ions.

[0052] Step 1.1, select the substrate layer 1.

[0053] Further, the substrate layer 1 is bulk silicon.

[0054] Step 1.2, doping P-type ions in the substrate layer 1 to obtain a P-type doped substrate layer 1 .

[0055]Step 2, preparing a stop layer 2 and several sidewalls 3 having the same shape and size as the predetermined cross-section of the fin on the ...

Embodiment 2

[0081] On the basis of Example 1, this example introduces the preparation method of the FinFET device resistant to single event effect provided by the present invention in a specific implementation manner. The preparation method includes:

[0082] Step 1. Preparation of silicon substrate.

[0083] Specifically, P-type ions are doped into the silicon substrate to form a P-type silicon base, which is the substrate layer.

[0084] Step 2. SiO 2 Side wall preparation.

[0085] Specifically, Si was deposited on silicon substrates using plasma-enhanced chemical vapor deposition 3 N 4 To form a mask layer, the mask layer is a stop layer, and SiO is deposited on the mask layer using atomic layer deposition 2 , and then etched SiO by reactive ion etching 2 , forming several SiO 2 side wall.

[0086] Step 3, preparation of the active region.

[0087] Specifically, with SiO 2 The sidewall is a hard mask, and the silicon substrate is etched by a self-aligned double imaging method...

Embodiment 3

[0097] On the basis of Example 1, this example introduces the preparation method of the FinFET device resistant to single event effect provided by the present invention in a specific implementation manner. The preparation method includes:

[0098] Step 1. Preparation of silicon substrate.

[0099] Specifically, P-type ions are doped into the silicon substrate to form a P-type silicon base, which is the substrate layer.

[0100] Step 2. SiO 2 Side wall preparation.

[0101] Specifically, Si was deposited on silicon substrates using plasma-enhanced chemical vapor deposition 3 N 4 To form a mask layer, the mask layer is a stop layer, and SiO is deposited on the mask layer using atomic layer deposition2 , and then etched SiO by reactive ion etching 2 , forming several SiO 2 side wall.

[0102] Step 3, preparation of the active region.

[0103] Specifically, with SiO 2 The sidewall is a hard mask, and the silicon substrate is etched by a self-aligned double imaging method t...

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Abstract

The invention discloses a single-event effect-resistant FinFET device and a preparation method thereof. The preparation method includes: preparing a substrate layer doped with ions; preparing a stop layer on the substrate layer and a plurality of fins with preset cross-sectional shapes and Spacers of the same size; etch the stop layer and the substrate layer to form several fins on the remaining substrate layer; perform local oxidation on the corners where the fins connect to the substrate layer; prepare a blanket stop layer on the stop layer and the substrate layer and the oxide layer of the substrate layer; planarizing the oxide layer to expose the upper surface of the stop layer; etching a part of the oxide layer to retain the oxide layer at a predetermined height on the substrate layer; removing the stop layer on the fin; depositing a gate oxide layer on the fin; depositing a gate on the gate oxide layer. The FinFET device prepared by the invention makes the current channel of the single event effect of the FinFET longer, reduces the gain of the parasitic transistor, thereby effectively avoiding the single event effect of the FinFET.

Description

technical field [0001] The invention belongs to the technical field of semiconductor devices, and in particular relates to a single-event-resistant FinFET device and a preparation method. Background technique [0002] With the development of semiconductor technology, FinFET (Fin Field-Effect Transistor, Fin Field Effect Transistor) devices appear and develop into the mainstream technology of semiconductor manufacturing and are widely used in integrated circuits. After verification by integrated circuit foundries, 22nm technology The node's FinFETs can deliver up to 37% performance improvement at low voltages and consume less than half the power of 32nm planar transistors. Because of their low leakage current, excellent short-channel characteristics and compatibility with existing fabrication processes of bulk silicon (Bulk) and silicon-on-insulator (SOI) technologies. FinFET was first proposed by Professor Hu Zhengming, and was first successfully used by Intel Corporation i...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/06H01L21/336
CPCH01L29/0684H01L29/66795H01L29/785
Inventor 张春福张泽阳成亚楠张进成郝跃
Owner XIDIAN UNIV