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Verification platform and verification method suitable for ECC function verification of network switching chip

A network switching and functional verification technology, which is applied in the verification platform field of network switching chip ECC function verification, can solve the problems of limited ECC function coverage and high cost, and achieve the effects of easy EDA simulation implementation, high verification efficiency, and easy implementation

Active Publication Date: 2021-03-16
PLA STRATEGIC SUPPORT FORCE INFORMATION ENG UNIV PLA SSF IEU
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] In order to overcome the problem that the ECC function coverage of the FPGA prototype verification scheme is limited and the cost is high, the present invention provides a verification platform and a verification method suitable for the verification of the ECC function of the network switching chip, and realizes that the network switching chip has complete and efficient ECC functions. Sufficient verification, with the advantages of strong operability, simple implementation, and comprehensive functional coverage

Method used

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  • Verification platform and verification method suitable for ECC function verification of network switching chip
  • Verification platform and verification method suitable for ECC function verification of network switching chip
  • Verification platform and verification method suitable for ECC function verification of network switching chip

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Embodiment 1

[0044] Such as figure 1 As shown, the embodiment of the present invention provides a kind of verification platform suitable for network exchange chip ECC function verification, including: configuration information adding module, error injection module and error checking comparison module; wherein, configuration information adding module is used in existing Add configuration information and error injection type information on the verification platform; the configuration information includes whether to enable the status information of the ECC function and whether to enable the status information of the interrupt function; the error injection type information includes: ECC error type; the error injection module is used for According to the configured ECC error type, error injection is performed into the network switch chip under test (DUT); the error checking and comparison module is used to obtain the expected output result of the network switch chip under test in advance accordi...

Embodiment 2

[0048] Correspondingly, the embodiment of the present invention also provides a verification method suitable for verifying the ECC function of the network switching chip, which can be applied to the verification platform provided in the above embodiment, and the verification method includes:

[0049] S101: For different ECC error types, perform error injection into the network switch chip to be tested according to the preset error injection method, and then perform ECC function verification on the network switch chip to be tested according to the preset error check comparison method; the ECC Error types include: single-bit error, two-bit error and no ECC error;

[0050] S102: Inject random ECC error types into the network switch chip to be tested, and then perform ECC function verification on the network switch chip to be tested according to a preset error checking and comparison method.

[0051] Specifically, in order to ensure that the ECC function in the DUT of the device u...

Embodiment 3

[0066] On the basis of Example 2, such as image 3 As shown, the embodiment of the present invention provides another verification method applicable to the ECC function verification of the network switching chip, comprising the following steps:

[0067]S301: Ensure that when no ECC error occurs on the DUT, that is, when no ECC error is injected, the DUT has no functional problems and no interruption is reported.

[0068] S302: Randomly inject single-bit errors, the position of single-bit errors covers both data bits and parity bits, complete a round of regression of all test cases, and confirm that the DUT has no functional problems; at the end of the simulation, the state of the ECC1-bit error count The expected result of the register is equal to the number of fault injections. If the verification result is inconsistent with this, it means that the ECC function of the DUT is defective, and further analysis and positioning is required in combination with the simulation wavefo...

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Abstract

The invention provides a verification platform and a verification method suitable for ECC function verification of a network switching chip. The verification platform comprises: a configuration information adding module used for adding configuration information and error injection type information to an existing verification platform; the error injection module that is used for performing error injection on the to-be-tested network switching chip according to the configured ECC error type; the error checking and comparing module that is used for obtaining an expected output result and interruption report information of the to-be-tested network switching chip in advance according to the type of the ECC error injected into the to-be-tested network switching chip, receiving an actual output result of the to-be-tested network switching chip, monitoring actual interruption report information of the to-be-tested network switching chip, and comparing the expected output result and the interruption report information with the actual output result and the interruption report information. The invention is high in verification efficiency, functional point verification coverage is more complete, and EDA simulation is easy to achieve.

Description

technical field [0001] The invention relates to the field of information technology, in particular to a verification platform and a verification method suitable for verifying the ECC function of a network switching chip. Background technique [0002] As the size of semiconductors becomes smaller and smaller, especially after entering the nanometer size, the power supply voltage continues to decrease and the operating frequency continues to increase, which makes the node capacitance between devices continue to decrease, and the memory is more and more vulnerable to high-energy radiation particles in the radiation environment. A soft error occurs on the affected page, which will cause the stored "0" and "1" to flip, resulting in a decrease in memory reliability. In order to improve the ability of integrated circuits to resist soft failures and improve design reliability, ECC (Error Correction Code, error correction code) design is usually used to detect and correct soft errors...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/26G06F11/22G06F11/10
CPCG06F11/26G06F11/2215G06F11/1044
Inventor 刘冬培沈剑良刘勤让宋克魏帅虎艳宾张霞陈艇李沛杰张丽
Owner PLA STRATEGIC SUPPORT FORCE INFORMATION ENG UNIV PLA SSF IEU
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