Dummy Gate Cutting Process and Resulting Gate Structures
A technology of dummy gates and gates, applied in the direction of electrical components, transistors, electric solid devices, etc., can solve the problems of increasing the thickness of the effective gate dielectric and the difficulty of creating an inversion layer
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example 1
[0066] Example 1 is a method for forming a semiconductor structure comprising: forming a dummy gate stack; etching the dummy gate stack to form an opening; depositing a first dielectric layer extending into the opening; depositing a second dielectric layer on the dielectric layer, and extending the second dielectric layer into the opening; performing a planarization process to form a gate isolation region including the first dielectric layer and the second dielectric layer; removing portions of the dummy gate stack on opposite sides of the gate isolation region to form trenches; performing a first etch process to remove sidewall portions of the first dielectric layer; performing a second an etching process to thin the second dielectric layer; and forming a replacement gate in the trench.
[0067] Example 2 is the method of example 1, wherein, in the first etching process, the first dielectric layer has a higher etch rate than the second dielectric layer, and in the second etch...
example 8
[0073] Example 8 is a semiconductor structure, including: a first semiconductor region and a second semiconductor region; a first gate stack and a second gate stack, the first gate stack and the second gate stack are respectively located at the On the first semiconductor region and the second semiconductor region; a dielectric region, the dielectric region is located between the first semiconductor region and the second semiconductor region; and a gate isolation region, the gate isolation region between the first gate stack and the second gate stack, wherein the bottom surface of the gate isolation region contacts the dielectric region, and wherein, in plan view of the gate isolation region, The gate isolation region has recessed sidewalls in contact with the first gate stack and the second gate stack.
[0074] Example 9 is the structure of Example 8, further comprising: a first gate spacer and a second gate spacer located between the gate isolation region on the opposite sid...
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