Magnetic random access memory architecture

A random access memory and magnetic technology, applied in the field of memory, can solve the problems of inapplicability of magnetic random access memory, incompatibility, etc., and achieve the effect of increasing memory capacity, increasing molding density, and simplifying manufacturing process

Active Publication Date: 2021-05-07
SHANGHAI CIYU INFORMATION TECH
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Method used

[0069] In some embodiments, both ends of the repeating unit group at the end of the same word line 08 are provided with the gate connection unit 30, or the gate connection unit 30 is provided at any end thereof, which is used for Reduce the impedance on the gate connection.
[0076] In some embodiments, the uppermost part of the substrate contact unit 34 and the source connection unit ...
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Abstract

The invention provides a magnetic random access memory architecture, and the architecture comprises a plurality of memory units, and the memory units are respectively arranged on bit lines and word lines which are parallel to each other and are positioned in areas where the bit lines and the word lines intersect with gate lines respectively. The plurality of storage units form a plurality of repeatable unit groups and at least one group of substrate contact units; each repetitive unit group is also provided with at least one source electrode connecting unit along the bit line direction; each repeating unit group is provided with at least one gate connection unit along the word line direction. Through the design of the repeating unit group, the manufacturing process of the memory can be simplified, and the vertical field effect transistor can be compatible with the fin-shaped design, the memory unit forming density of the memory can be improved, and the memory capacity of the memory can be improved.

Application Domain

Solid-state devicesDigital storage +1

Technology Topic

Storage cellEngineering +6

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  • Magnetic random access memory architecture
  • Magnetic random access memory architecture
  • Magnetic random access memory architecture

Examples

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Example Embodiment

[0043] The following descriptions of the various embodiments refer to the accompanying drawings to illustrate specific embodiments in which the invention may be practiced. The directional terms mentioned in the present invention, such as "up", "down", "front", "rear", "left", "right", "inside", "outside", "side", etc., are only for reference Additional schema orientation. Therefore, the directional terms used are used to describe and understand the present invention, but not to limit the present invention.
[0044] The drawings and descriptions are to be regarded as illustrative in nature and not restrictive. In the figures, structurally similar elements are denoted by the same reference numerals. In addition, the size and thickness of each component shown in the accompanying drawings are arbitrarily shown for understanding and ease of description, but the present invention is not limited thereto.
[0045] In the drawings, the configuration ranges of devices, systems, components, and circuits are exaggerated for clarity, understanding, and ease of description. It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present.
[0046] Additionally, in the specification, unless explicitly described to the contrary, the word "comprising" will be understood to mean the inclusion of stated components, but not the exclusion of any other components. Also, in the specification, "on" means above or below the target component, and does not mean necessarily on top based on the direction of gravity.
[0047] In order to further illustrate the technical means and effects adopted by the present invention to achieve the predetermined purpose of the invention, the following describes a magnetic random access memory architecture proposed according to the present invention, its specific implementation, structure, features and Its effect is described in detail as follows.
[0048] figure 1 A schematic diagram of an exemplary magnetic random access memory cell structure. like figure 1 As shown, a schematic diagram of a magnetic tunnel junction in a low-resistance state 01 and a high-resistance state 02 is shown. The magnetic random access memory (MRAM) includes a memory layer 03, a tunnel barrier layer 04 and a reference layer 05, and the process of reading the magnetic random access memory (MRAM) is to measure the resistance of the magnetic tunnel junction 07 (MTJ). With the newer STT-MRAM technology, writing to the magnetic tunnel junction 07 is also simpler: a write operation is performed through the magnetic tunnel junction 07 using a stronger current than reading. A bottom-up current orients the variable magnetization layer parallel to the pinned layer, and a top-down circuit orients it antiparallel.
[0049] figure 2 A schematic diagram of a magnetic tunnel junction structure in an exemplary magnetic random access memory cell. like figure 2 As shown, the most basic magnetic random access memory (MRAM) storage unit is composed of a magnetic tunnel junction 07 and a MOS transistor. The gate of the MOS transistor is connected to the word line 08 of the chip, which is responsible for turning on or off the unit, and the magnetic tunnel junction 07 and the MOS transistor are connected in series on the bit line 06 of the chip. Read and write operations are performed on bit line 06.
[0050] image 3 A schematic diagram of an exemplary three MR memory cell structure. like image 3 As shown, the metal oxide semiconductor tube is generally an NMOS tube made by a standard etching process, with a P-type semiconductor substrate 12 as the base, the magnetic tunnel junction 07 is connected to the drain 20 through the via/connection point 10, and the drain 20 and the source are connected. The poles 19 are all N+ doped regions 11 , the other end of the magnetic tunnel junction 07 is connected to the bit line 06 , and the N+ doped regions 11 are located on the P-type semiconductor substrate 12 .
[0051] Figure 4 It is an exemplary magnetic random access memory chip architecture diagram. like Figure 4 As shown, a magnetic random access memory (MRAM) chip consists of one or more arrays 13 of magnetic random access memory (MRAM) memory cells, each array 13 has several external circuits, such as: row address decoder 15: Address S01 becomes the selection of word line 06, column address decoder 14: turns the received address S01 into the selection of bit line 06, read and write control 17: controls the read (measurement) write (current applied) on bit line 06 Operation, input and output control 18: Exchange data with external S03.
[0052] Figure 5 A schematic diagram of an exemplary 3D magnetic random access memory cell structure of FINFET technology. like Figure 5 As shown, the metal-oxide-semiconductor technology of higher process nodes (below 14 nm) has adopted FINFET, and the metal-oxide-semiconductor transistor has been semi-stereoscopic, which can provide satisfactory performance at a smaller plane size. The channel of the FINFET metal oxide semiconductor transistor is established on the three-dimensional Fin (fin structure) 22, and the gate 21 surrounds the Fin (fin structure) 22 on three sides.
[0053] Figure 6A and Figure 6B The conceptual schematic diagram of the storage array structure according to the embodiment of the present application is shown, please cooperate with subsequent figures in advance to facilitate understanding. The memory array structure includes a plurality of memory cells, and the plurality of memory cells are respectively disposed on the bit line 06 and the word line 08 which are parallel to each other, and are located at the intersection of the bit line 06 and the word line 08 with the gate line 21 respectively region, each memory cell includes a vertical field effect transistor combined with a fin structure and a magnetic tunnel junction 07, wherein the plurality of memory cells form a plurality of repeatable cell groups and at least one set of substrate contact cells; along the bit line 06 At least one source connection unit 35 is arranged in each repeating unit group along the direction of the word line 08 ; at least one gate connection unit 30 is arranged in each repeating unit group along the direction of the word line 08 .
[0054] In some embodiments, the connection unit is configured according to each repeating unit group, and refers to all parts that realize the source and gate connection.
[0055] The bottom of the memory array structure is a semiconductor region 25, the semiconductor region 25 is divided into several regions, the middle is the effective region of the memory array, the location of the array formed by the memory cells is arranged, and it is an N-type doped region. The upper and lower sides are P-type doped regions, which are mainly arranged as the positions of the substrate contact units 34 . For the repeating unit group connected to the same word line 08, one memory cell space at one end is occupied to generate the gate connection unit 30. In general, the word line 08, the bit line 06 and the source line 27 are designed in parallel, and are perpendicular to the gate line 21 (including the dummy gate line). In fabrication, the memory cell (repeating cell group), the gate connection unit 30 and the substrate contact unit 34 are formed in the same process.
[0056] Figure 7A A schematic diagram of a storage unit of a magnetic random access memory architecture according to an embodiment of the present application, Figure 7B The cross-sectional view of the memory cell in the embodiment of the present application is perpendicular to the word line, please cooperate and understand at the same time. The magnetic random access memory structure includes a plurality of memory cells, and each memory cell includes: a semiconductor region 25 of a first doping type; a fin structure 23 disposed on the semiconductor region 25, and the fin of the fin structure 23 The part is of the second doping type, the top of the fin structure 23 is of the first doping type as the drain 32, the bottom end of the fin structure 23 contacts the source formed by the semiconductor region 25; the gate 21 , disposed on both sides of the fin structure 23, the gate 21 isolates the fin structure 23 and the semiconductor region 25 through an insulating medium 26; the semiconductor region 25, the fin structure 23 and the The gate 21 forms a fin-shaped vertical field effect transistor structure; the insulating medium is silicon oxide; and the magnetic tunnel junction 07 is connected to the drain 32 through the conductive element 24 .
[0057] In some embodiments, the first doping type is N++ type and the second doping type is P type.
[0058] In some embodiments, the semiconductor region 25 is formed on a silicon wafer 38 .
[0059] In some embodiments, the source connecting unit 35 and the gate connecting unit 30 are connected through the metal layer of the conductive component 24.
[0060] In some embodiments, the fin structure 23 is used as a conductive channel, and its interior is P-type doped. The gate 21, the fin structure 23 and the semiconductor region 25 form a vertical metal oxide semiconductor field effect transistor (MOSFET, MOS transistor for short). The gate 21 controls the opening or closing of the conduction channel of the MOS transistor.
[0061] In some embodiments, the source lines 27 are formed by connecting the semiconductor regions 25 of the plurality of memory cells. The formation method of the source line 27 can be selectively adopted: (1) a plurality of memory cells, the fin structures 23 of which are parallel, can be connected to the same bit line 06, and are regarded as the same row; the semiconductor regions 25 of the memory cells in the same row are connected to each other , to form source lines 27 corresponding to memory cells in the same column; (2) the semiconductor regions 25 in several columns can be connected to form a common source line 27 .
[0062] Figure 7C A side view of the magnetic random access memory cell of an embodiment of the present application is parallel to the word line. In some embodiments, one of the fin structures 23 can be extended to form a row structure.
[0063] In some embodiments, the word line 08 is formed by connecting the gate 21 along the fin portion of the fin structure 23 . As mentioned above, the gate 21 is extended along with the fin structure 23, and it can also be considered that the gate 21 of each memory cell is connected to each other in structure.
[0064] The difference between the present application and the common fin field effect transistor (Fin Field-Effect Transistor, FINFET) is that the gate and the fin structure in the FINFET are perpendicular to each other, and the gate 21 disclosed in the present application grows along the fin structure 23 , the semiconductor region 25 on the silicon wafer is connected to form a source line 27 , and the bit line 06 is perpendicular to the fin structure 23 and the word line 08 . In the memory cell, the gate 21 is on both sides of the fin structure 23 .
[0065] like 7A to 7C As shown, in some embodiments, the top of the magnetic tunnel junction 07 contacts the bit line 06, and is electrically connected to the top of the fin structure 23 through the conductive element 24, that is, the aforementioned drain.
[0066] In some embodiments, the conductive components 24 are vias or contacts, and the materials thereof include titanium, tantalum, tungsten, titanium nitride, tantalum nitride, and combinations thereof.
[0067] Figure 7DA side view of the magnetic random access memory cell of an embodiment of the present application is parallel to the word line. In an embodiment of the present application, a plurality of repeating unit groups are connected to the same word line 08 in a repeating configuration, each repeating unit group includes the plurality of memory cells (bit lines) 36, and one end of the repeating unit group is a The space of one memory unit 36 ​​is used to generate the gate connection unit 30, and the metal layer 31 is disposed on the top of the gate connection unit 30 instead of the magnetic tunnel junction 07; wherein, the plurality of repeating unit groups pass through the gate The electrode connecting unit 30 is a boundary, the gates 21 are connected along the fins to form the same word line 08 , and the sources of the semiconductor regions of the memory cells (bit lines) 36 are connected to form a source line 27 .
[0068] That is to say, when the capacity of the memory cell is fixed, the density of the gate connection points can be changed by adjusting the number of tubes in the memory cell, thereby improving the impedance on the gate connection.
[0069] In some embodiments, both ends of the repeating unit group at the end of the same word line 08 are provided with the gate connection unit 30 or at either end thereof, which is used to lower the gate impedance on the wire.
[0070] Figure 7E This is a side view of a magnetic random access memory cell parallel to a bit line according to an embodiment of the present application.
[0071] In an embodiment of the present application, the substrate contact unit 34 and the repeating unit groups are arranged parallel to the direction of the same bit line 06 , and the substrate contact unit 34 is not connected to the same bit line 06 is connected, and the substrate contact unit 34 is disposed at one end of the same bit line 34, including: the semiconductor region 25, disposed on the substrate (silicon wafer 38). The fin structure 23 is disposed on the semiconductor region 25 , the top of the fin structure 23 is connected to a conductive element (contact 24 ), and the bottom end of the fin structure 23 is in contact with the semiconductor region 25 ; the gate 21 , disposed on both sides of the fin structure 23, the gate 21 isolates the fin structure 23 and the semiconductor region 25 through an insulating medium; and, the metal layer 31 connecting the conductive components (contacts 24), wherein , the semiconductor region 25 and the fin structure 23 are of the second doping type.
[0072] Each repeating unit group includes a memory cell group region 37, which has the plurality of memory cells, one end of the repeating unit group occupies one memory cell space for generating the source connection unit 35, and the metal layer 31 is provided instead of the magnetic tunnel junction 07 At the top of the source connecting unit 35, the fins of the source connecting unit 35 are replaced with the first doping type; wherein the plurality of repeating unit groups are demarcated by the source connecting unit 35, and the The source electrodes of the semiconductor regions 225 of the plurality of repeating unit groups are connected to form a source electrode line 27 . In some embodiments, the number of tubes in the memory cell group area can be adjusted according to circuit performance indicators.
[0073] In an embodiment of the present application, both ends of the repeating unit group at the end of the same bit line 06 are provided with the source connection unit 35 or the source connection unit 35 is provided at either end thereof, thereby adjusting Chip electrical characteristics.
[0074] In some embodiments, the end of the same bit line end is provided with the substrate contact unit 34 .
[0075] In some embodiments, the source connection unit 35 needs to be doped with a high concentration of N-type strong ion implantation to change the P-doped region into an N-doped region.
[0076] In some embodiments, the top of the substrate contact unit 34 and the source connection unit 35 are connected out through the metal layer 31 to facilitate internal wiring.
[0077] In an embodiment of the present application, the aforementioned various types of semiconductor materials include silicon (Si) materials or silicon carbide (SiC) materials.
[0078] In an embodiment of the present application, the insulating medium and the dielectric can optionally be made of silicon dioxide or benzocyclobutene (BCB) or polyimide (PI), silicon dioxide and other substances. Composite layers, such as composite layers of silicon dioxide and silicon nitride, composite layers of silicon dioxide and polyimide (PI), etc. insulating materials.
[0079] 8A to 8G This is a schematic diagram of structural changes in the manufacturing process of the memory cell according to the embodiment of the present application. A method for manufacturing a magnetic random access memory, comprising at least the following steps:
[0080] like Figure 8A As shown, semiconductor regions 25 of the first doping type are formed in the semiconductor substrate 12 of the second doping type. In some embodiments, the semiconductor region 25 is formed in the semiconductor substrate 12 by ion implantation.
[0081] like Figure 8B As shown, the semiconductor substrate 12 is etched to form a fin structure 23 on the surface of the semiconductor substrate 12. In some embodiments, the bottom of the fin structure 23 is formed by etching the semiconductor region 25 .
[0082] like Figure 8C As shown, an insulating medium 26 is formed on the surface of the fin structure 23 . A gate 21 is formed on the periphery of the fin structure 23 , and the fin structure 23 is isolated from the fin structure 23 and the semiconductor region 25 by the insulating medium 26 .
[0083] like Figure 8D As shown, the semiconductor region 25 and the fin structure 23 are covered by an insulating medium 26. The insulating medium is formed of insulating material, dielectric material, such as silicon oxide. Wherein, the semiconductor region 25, the fin structure 23 and the gate 21 form a fin-shaped vertical field effect transistor structure.
[0084] like Figures 8E to 8G As shown, the insulating medium 26 and the gate electrode 21 are etched in part, and then the insulating medium 26 is filled to form an etched hole 29 that exposes part of the fin structure 23.
[0085] like Figure 8E It is shown that, in some embodiments, in the step of etching the insulating medium 26 and the gate 21 of the portion, the etching portion corresponds to the bit line 06. At the location of the bit line 06 is an etched groove, which exposes part of the gate 21 (word line) by etching.
[0086] like Figure 8F It is shown that, in some embodiments, the gate 21 is further selectively etched in the etched groove, so that a small part of the fin structure 23 is exposed.
[0087] like Figure 8G It is shown that, in some embodiments, a long groove is etched, and the exposed part of the fin structure 23 and the gate 21 is refilled with an insulating medium 26 (or a dielectric). In the original etching of the long groove, it is necessary to make conductive components. An etched hole 29 is formed in place to expose the fin structure 23 .
[0088] Conductive elements 24 are formed in the etched holes 29 . In some embodiments, the step of forming the conductive element 24 in the etched hole 29 further includes: doping the first doping type ( such as N++ doping); and filling the etched holes 29 with conductive materials to form the conductive components 24 . However, if necessary, the surface of the conductive component 24 may be polished flat, such as by chemical mechanical polishing (Chemical Mechanical Polishing, CMP) means to polish the surface of the conductive component 24.
[0089] After that, a magnetic tunnel junction 07 is formed above the conductive element 24, and the magnetic tunnel junction 07 is connected through the bit line 06, the structure is as follows 7A to 7C shown.
[0090] like 7A to 7C , a magnetic random access memory structure of the present application includes a plurality of storage cells, each storage cell is arranged at the intersection of the bit line 06 and the word line 08, and it is characterized in that, each storage cell includes: N++ type doped semiconductor A region 25, the semiconductor regions 25 of the plurality of memory cells are adjacent to form a source line 27; a P-type doped fin structure 23 is arranged above the semiconductor region 25, and the top of the fin structure 23 is arranged as a drain The bottom end of the fin structure 23 is in contact with the source formed by the semiconductor region 25; the gate 21 is partially arranged around the periphery of the fin structure 23, and the top of the gate 21 is provided with an opening for the The drain contacts the conductive element 24, the gate 21 is separated from the fin structure 23, the conductive element 24 and the semiconductor region 25 by an insulating medium, such as silicon oxide, the gate 21, the fin The source formed by the like structure 23 and the semiconductor region 25 forms a vertical field effect transistor, the gate 21 controls the opening or closing of the conduction channel of the vertical field effect transistor, and the gates 21 of the plurality of memory cells The word lines 08 are formed adjacent to each other; and a magnetic tunnel junction 07 is disposed above the fin structure 23 to connect the bit lines 06 and the conductive elements 24 .
[0091] In an embodiment of the present application, the gate and the conductive element are formed of conductive materials, which include polysilicon or metal materials with conductive capability.
[0092] In an embodiment of the present application, the aforementioned various types of semiconductor materials include silicon (Si) materials or silicon carbide (SiC) materials.
[0093] In an embodiment of the present application, the insulating medium and the dielectric can optionally be made of silicon dioxide or benzocyclobutene (BCB) or polyimide (PI), silicon dioxide and other substances. Composite layers, such as composite layers of silicon dioxide and silicon nitride, composite layers of silicon dioxide and polyimide (PI), etc. insulating materials.
[0094] like Figure 6A and Figure 6B The conceptual schematic diagram of the storage array structure of the embodiment of the present application is shown, please cooperate with 7A to 8G to facilitate understanding. As mentioned above, the semiconductor region 25 is divided into several regions, the middle is the effective region of the memory array, the position of the array formed by the memory cells is arranged, and it is the N-type doped region. The upper and lower sides are P-type doped regions, which are mainly arranged as the positions of the substrate contact units 34 . For the repeating unit group connected to the same word line, one memory cell space at one end will be occupied to generate the gate connection unit 30 . On the whole, the word lines, bit lines and source lines are designed in parallel, and are perpendicular to the gate lines (dummy gate lines). In fabrication, memory cells (repeated cell groups), gate connection cells and substrate contact cells are formed in the same process. please cooperate 6A to 8G and the preceding instructions to understand the following process instructions:
[0095] see Figure 8A and Figure 8B In this way, N-type and P-type semiconductor regions are formed as the aforementioned N-type active regions and P-type edge regions, and fin structures are formed thereon.
[0096] see Figure 8C and Figure 8D In this way, gates are formed on both sides of the fin structure, and the semiconductor region, the fin structure and the gate form a fin-shaped vertical field effect transistor structure.
[0097] see Figures 8E to 8G way to form a conductive component and a magnetic tunnel junction, so far, the combination Figure 8A to Figure 8G , the general structure of the memory unit (repeated unit group), the gate connection unit and the substrate contact unit has been formed. After that, the metal layout of the bit line, word line and source line is performed, that is, the Figure 6B Example of storage array structure shown.
[0098]In the present application, the gate is formed along the fin-shaped structure, so that the vertical field effect transistor is compatible with the fin-shaped design, and at the same time, the forming density of the memory cells of the memory is increased, which is helpful for the improvement of the memory capacity of the memory.
[0099] The terms "in one embodiment of the present application" and "in various embodiments" are used repeatedly. This term does not generally refer to the same embodiment; however, it can also refer to the same embodiment. The terms "comprising", "having" and "including" are synonymous unless the context of the text indicates otherwise.
[0100] The above are only specific embodiments of the present application, and are not intended to limit the present application in any form. Although the present application has been disclosed above with specific embodiments, it is not intended to limit the present application. , within the scope of the technical solution of the present application, when the technical content disclosed above can be used to make some changes or modifications to equivalent embodiments of equivalent changes, but all content that does not depart from the technical solution of the present application, according to the technical solution of the present application Substantially any simple modifications, equivalent changes and modifications made to the above embodiments still fall within the scope of the technical solutions of the present application.

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