Real-time FPGA error detection method based on standard input and output verification

Abstract

The invention discloses a real-time FPGA error detection method based on standard input and output verification. The real-time FPGA error detection method comprises the following steps of 1, acquiring key data information of an interlaced adjoint circuit A` in each detection object module A at an FPGA end, 2, acquiring processing time information, input data and output data of an interlaced adjoint circuit through calculation according to the data information obtained in the step 1, 3, respectively importing the data information obtained in the step 1 and the step 2 into a coprocessor end, and carrying out real-time monitoring on the state of each interlaced adjoint circuit at the FPGA end, and 4, after an error is monitored, counting error information of each interlaced adjoint circuit according to an error detection method, and indicating an error module in the detection object circuit. According to the method, hardware platform information is monitored in real time through the coprocessor end, whether the SEU effect occurs in the module circuit to be detected or not can be accurately detected after experimental verification, and the method is completely suitable for the actual detection requirement of the SEU effect in FPGA equipment.

Description

technical field [0001] The invention belongs to the technical field of on-chip system detection, and in particular relates to a real-time FPGA error detection method based on standard input and output verification, which is used for fault detection and analysis of the single event effect of the FPGA system. Background technique [0002] Large-scale Field Programmable Gate Array (FPGA) is widely used in aerospace engineering because of its flexible design, short development cycle, and low cost. However, with the continuous development of integrated circuit technology, the integration level continues to increase. , Nano-scale integrated circuits are subject to system failures such as logic state reversal or circuit failure caused by high-energy particle collisions, which seriously affect the reliability and safety of electronic equipment. Therefore, in view of the increasingly serious single event effect problem, it is very important to improve the reliability of FPGA equipmen...

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Problems solved by technology

[0006] The purpose of the present invention is to address the above-mentioned deficiencies in the prior art, to propose a real-time FPGA error detection method based on standard input and output verification, and to monitor the hardware platform information online in real time through the coprocessor side, so as to solve the detection problems existing in the prior art Technical problems of incomplete content and probability of faults being concealed in self-detection circuits

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