Inter-chip interconnection bypass system of interconnected bare chip and communication method of inter-chip interconnection bypass system

Abstract

The invention relates to an inter-chip interconnection bypass system of interconnected bare chips and a communication method of an inter-chip interconnection bypass system. The inter-chip interconnection bypass system of the interconnected bare chips comprises a bypass path, a first bypass controller and a second bypass controller which are arranged in the interconnected bare chips, the first bypass controller is connected with a first synchronous controller of the interconnected bare chips and a bare chip network, the second bypass controller is connected with a second synchronous controller of the interconnected bare cores and the bare chip network, the bypass path is connected with the first bypass controller and the second bypass controller, the first bypass controller and the second bypass controller are used for sending data entering one synchronous controller to the other synchronous controller through the bypass path and outputting the data to the outside of the interconnected bare chips when the data need to cross the current interconnected bare chips. The system can realize transmission around the bare chips, is short in delay and high in transmission efficiency across the bare chips, can enlarge the interconnection scale of the bare chips, and is simple in circuit structure, small in hardware overhead, high in expandability and efficient in communication.

Description

technical field [0001] The invention relates to a communication system between bare chips, in particular to an inter-chip interconnect bypass system for interconnecting bare chips and a communication method thereof. Background technique [0002] With the development of digital integrated circuits, system-on-chip (Systemon Chip, SoC, refers to the integration of multiple functional modules on the same silicon chip) has almost become a necessary solution to achieve high-performance systems, manufacturers continue to expand the scale of SoC by To meet the user's demand for product performance. However, limited by factors such as processing technology, Moore's Law (that is, the law that the number of transistors that can be accommodated on an integrated circuit doubles every 24 months) is gradually failing, which makes it difficult to expand the scale of integrated circuits on a single silicon wafer. Costs and development cycles become extremely high. [0003] In the future, i...

AI Technical Summary

Problems solved by technology

For data that needs to be transmitted across multiple bare cores, this transmission method causes a huge time delay, reduces communication efficiency, and is not conducive to expanding the interconnection scale of bare cores

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