High-speed high-voltage word line driving circuit oriented to a storage and calculation array
A technology of word line driving and high voltage, which is applied in the field of high-speed high-voltage word line driving circuits, can solve the problems of unsuitable storage and calculation arrays, achieve good symmetry, and reduce the effect of layout area
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Embodiment 1
[0033] In input / read mode: when the voltage at the input terminal of the high-voltage control circuit is in_REA=VDD, in_CTR=GND, in_ERA=GND, the output terminal of the level control circuit has V REA = first positive high voltage, V ERA =GND,V CTR =GND; at this time, for the word line gating circuit, it works in the voltage domain of GND-the first positive high voltage, the interlock structure of M1 and M2 passes through the transmission tube M10, and finally the load capacity is enhanced through the inverter to realize the input of GND -VDD to output GND-level conversion of the first positive high voltage, and M5, M6, M7, M8 due to the existence of the transmission tube M9, by adjusting the Bulk potential to GND, avoiding the short circuit caused by the charge backflow.
[0034] In the input / read mode, the port voltage is shown in Table 1:
[0035]
Embodiment 2
[0037] In erasing mode: when the voltage at the input terminal of the high-voltage control circuit is in_REA=GND, in_CTR=VDD, in_ERA=VDD, the output terminal of the high-voltage control circuit has V REA = GND V, V ERA =VDDV,V CTR = first negative high voltage. At this time, for the word line gating circuit, it works in the voltage domain of the first negative high voltage-GND, and the interlock structure of M7 and M8 passes through the transmission tube M9, and finally through the inverter to enhance the load capacity, so as to realize the input from GND-VDD to Output the level conversion of the first negative high voltage-GND, and M1, M2, M3, M4 due to the existence of the transmission tube M10, by adjusting the Bulk potential to the first positive high voltage, avoiding the short circuit caused by the charge backflow.
[0038] In the erase mode, the port voltage is shown in Table 2:
[0039]
[0040] Assume that the input and read first positive high volta...
Embodiment 3
[0046] When the word line is in the working state of the word line gate in the input / read mode, when the in is 1.8V, in_REA is 1.8V, in_CTR is GDN, and in_ERA is GDN, the high voltage control circuit outputs V REA 10V, V ERA 0V, V CTR is GDN; the substrates of the word line gating circuits M1, M2 and M10 are 10V, and the substrates of other MOS transistors are 0V. The gate of M3 is 1.8V and works in the saturation region. Set the gate voltage of M2 to 0, so M2 is turned on, so that the gate of M1 and the source of M10 are placed at 10V, M1 is turned off, M10 is turned on, and the inverter The input of I1 is 10V, and the output is 0V; at this time, the drain of M9 is 10V. Since the substrate of M9 is GDN, it is in the off state, and the source voltage is clamped to around 1.8V, so M7 and M8 are both in the off state. .
[0047] The word line strobe port voltage in input / read mode is shown in Table 3:
[0048]
[0049] When the word line is in the input / read m...
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