Fan-out chip stacking packaging structure and manufacturing method thereof

Abstract

The invention provides a fan-out chip stacking packaging structure and a manufacturing method thereof. The fan-out chip stacking packaging structure comprises a stacking structure, a rewiring structure and a plurality of bump structures. The stacking structure comprises a plurality of stacking units which are stacked in sequence, the rewiring structure is arranged on one surface of the stacking structure, and the plurality of bump structures are arranged on the surface of one side, far away from the stacking units, of the rewiring structure. In one embodiment, chips disposed within the stacking units may have a plurality of rows of I / O ports, which are electrically connected to the plurality of bump structures through the rewiring structure.

Description

technical field [0001] The invention relates to a packaging structure. Specifically, it relates to a fan-out chip stack package structure and a manufacturing method thereof. Background technique [0002] At present, with the maturity of technology in the memory industry, the miniaturization of the memory package structure has become a major development trend. Since the characteristic size of the chip unit inside the package structure is gradually approaching the lower limit, in order to realize the miniaturization of the package structure, the requirements for the chip package technology are getting higher and higher. [0003] In the chip stacking packaging process in the prior art, the wire bonding process and the Through Silicon Via (TSV) process are mainly used, but in the face of the miniaturization requirements, these two packaging processes have some problems that need to be solved urgently . For example, when the wire bonding process is used for packaging, the pres...

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Problems solved by technology

For example, when the wire bonding process is used for packaging, the existence of gold fingers will expand the area of ​​the entire package structure by more than 20%, and the conductive path of the gold wire process is relatively long, which limits the high-frequency performance of the chipset

In addition, due to the longer production cycle required for packaging using the wire bonding process, more wire bonding machines are required to produce a certain number of packaging structures

Due to the limitation of the wiring method, the chips inside the package structure can only lead out the I / O terminals in a single row, which is not conducive to subsequent wiring operations

However, when the TSV process is used for packaging, the cooperation of chip design and chip packaging is required, which is technically difficult and the cost is relatively high.

Since the substrate in the package structure needs to have ultra-small pitch line width / spacing, the manufacturing cost will increase exponentially with the reduction of line width / spacing, and holes need to be drilled during the substrate manufacturing process, and these holes will be used in subsequent manufacturing. The process will not be filled with metal, which will increase a certain resistance, which will affect the high frequency performance of the product

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