An Acceleration System of Image Target Recognition Based on FPGA

Abstract

The invention discloses an FPGA-based image target recognition acceleration system; including an XDMA module integrated in the FPGA, a memory interface module, an acceleration core, a synchronization module and a control module, and an off-chip main memory connected to the FPGA, wherein the XDMA module, the It is used for data transmission between the upper computer and FPGA; the memory interface module is used to realize the logic function of controlling off-chip main memory read and write; the acceleration core is used for the accelerated operation of the algorithm; the synchronization module is mainly used to solve the problem of XDMA module and The problem of cross-clock domain data transmission between the acceleration core and the memory interface module is a control module, which is used to control the operation of the XDMA module, the memory interface module, the acceleration core, and the synchronization module. The present invention adopts a programmable FPGA to accelerate deep learning algorithms, and designs an acceleration system suitable for operating deep learning algorithms in the current mainstream image target recognition field.

Description

technical field [0001] The invention relates to the technical field of neural network, more specifically, it relates to an image target recognition acceleration system based on FPGA. Background technique [0002] Image target recognition technology is a research hotspot and difficulty in the field of computer vision. In recent years, deep learning algorithms have achieved breakthrough development and have been well applied in many fields. The application in the field of computer vision is advancing by leaps and bounds. The deep learning algorithm has gradually replaced the traditional image target recognition algorithm with its excellent performance. GF's deep learning algorithms applied to the field of image target recognition emerge in endlessly, such as R-CNN series algorithms, YOLO series algorithms , and SSD algorithms, etc. [0003] The traditional object recognition algorithm is based on the sliding window framework, which uses windows of different sizes to slide mu...

AI Technical Summary

Problems solved by technology

[0007] Although ASIC has great advantages in power consumption and size, the deep learning algorithm is developing rapidly and the model is updated frequently. The early development cost of ASIC is high and the flexibility is poor. Has certain research and development risks;

[0008] FPGA has low power consumption, small size, and programmability. It is easier to modify the deep learning algorithm that is in the stage of rapid development; the deep learning algorithm will bring a huge burden of storage, computing, and power consumption. The processor is not up to the task

Therefore, using dedicated hardware suitable for processing deep learning algorithms to accelerate deep learning algorithms is an effective solution

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