Processes for adjusting dimensions of dielectric bond line materials and related films, articles and assemblies

Abstract

The invention relates to processes for adjusting dimensions of dielectric bond line materials and related films, articles and assemblies. Processes for adjusting dimensions of dielectric bond line materials in stacks of microelectronic components, and related material films, articles and assemblies are described.

Description

[0001] priority claim [0002] This application claims an application filed on December 16, 2019, entitled "Processes for Adjusting Dimensions of Dielectric Bond Line Materials and Related Films, Articles and Assemblies" )” in the filing date of U.S. Patent Application No. 16 / 715,594. technical field [0003] Embodiments disclosed herein relate to methods of reducing the formation and extent of fillets on the periphery of dielectric bond wire material associated with stacked microelectronic assemblies. More particularly, embodiments disclosed herein relate to dimensioning dielectric bond wire films to reduce or eliminate the formation of peripheral fillets of bond wire material associated with thermocompression bonding of stacked microelectronic assemblies. Background technique [0004] Thermocompression bonding is a widely used technique for physically and electrically interconnecting vertically stacked microelectronic components (e.g., semiconductor die, semiconductor wa...

AI Technical Summary

Problems solved by technology

Therefore, the fillet of the dielectric material may also protrude upward and contaminate the bond head, but even if this does not happen, the presence of the fillet may compromise the integrity of the epoxy mold compound (EMC) on the side of the microelectronic assembly stack. Formation and integrity, causing flammability issues due to exposed dielectric films, or even extending between adjacent stacks of microelectronic components formed on a base substrate (e.g. base wafer), which can cause the aforementioned EMC issues and create Warpage of the substrate wafer

Such rounded corners result in non-linear component stack sides and other anomalies affecting the thickness and continuity of the EMC, singulating adjacent microelectronics in the event the dicing saw cuts along kerf lines that are not fully filled with EMC in the path of the dicing blade. damage to components

While current stacks of microelectronic components are typically separated by a reasonable distance of, say, about 600 μm, this distance continues to shrink as circuit density increases, allowing smaller microcomponent sizes and more closely spaced components per wafer.

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