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Signal processing circuit with channel ECC and memory

A signal processing circuit and channel technology, applied in information storage, static memory, digital memory information, etc., to achieve the effects of ensuring reliability, repairing data errors, and saving power consumption

Active Publication Date: 2021-06-25
CHANGXIN MEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] However, there is still room for improvement in terms of power consumption and reliability of existing memory data transmission lines with channel error detection and correction functions (linkError Correcting Code, linkECC). It is urgent to design a method that can reduce data transmission power consumption and improve storage reliability. The comprehensive performance of the existing ECC memory is further improved to meet the needs of various application scenarios

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  • Signal processing circuit with channel ECC and memory
  • Signal processing circuit with channel ECC and memory
  • Signal processing circuit with channel ECC and memory

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Embodiment Construction

[0045] With the advancement of technology, the integration of storage units in the memory is getting higher and higher, and the length of the data transmission line in the storage unit array is getting larger and larger. In the process of writing data to and reading data from the storage unit of the memory, The power consumption is getting higher and higher; in addition, the applicant finds that the ability of DRAM (Dynamic Random Access Memory, DRAM) to sense the high level is lower than the ability to sense the low level; Compared with low-level data, the leakage of low-level data is more serious.

[0046] In order to solve the above problems, an embodiment of the present application provides a signal processing circuit with channel ECC, which is used to write data and read data to the storage unit, including: an external data line, used to transmit data and ECC check code ; The error detection module is connected to the external data line, and is used to detect and / or corre...

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Abstract

The embodiment of the invention provides a signal processing circuit containing a channel ECC and a memory, and a data transmission line comprises an external data line used for transmitting data and an ECC check code; an error detection module which is used for carrying out error detection and / or error correction on the data transmitted in the external data line and outputting the corrected data; a judgment module which is used for outputting a first control signal; a statistical module which is used for outputting a second control signal; a data buffer module which is used for transmitting the corrected data output by the error detection module to a global data line or overturning the corrected data output by the error detection module and then transmitting the data to the global data line according to the first control signal; and a write-in module which is used for controlling the data in the global data line to be transmitted to the local data line and judging whether data overturning is carried out or not in the process of transmitting the data in the global data line to the local data line based on the third control signal. The invention aims to reduce the power consumption of the signal processing circuit, improve the reliability of data storage and the like.

Description

technical field [0001] The present application relates to the field of semiconductor circuit design, in particular to a signal processing circuit and memory with channel ECC. Background technique [0002] Dynamic Random Access Memory (DRAM) is widely used in modern electronic systems due to its high storage density and fast transmission speed. With the development of semiconductor technology, DRAM technology is becoming more and more advanced, and the integration of storage units is getting higher and higher; at the same time, various applications have higher and higher requirements on the performance, power consumption and reliability of DRAM. [0003] However, there is still room for improvement in terms of power consumption and reliability of existing memory data transmission lines with channel error detection and correction functions (linkError Correcting Code, linkECC). It is urgent to design a method that can reduce data transmission power consumption and improve stora...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/42G11C11/4078G11C11/4096
CPCG11C29/42G11C11/4078G11C11/4096Y02D10/00
Inventor 何军孙豳应战
Owner CHANGXIN MEMORY TECH INC