Memory and preparation method thereof

Abstract

The invention provides a memory and a preparation method thereof, and relates to the technical field of semiconductors. The memory comprises a substrate, wherein an isolation layer is arranged on the substrate, a plurality of bit lines are arranged in the isolation layer at intervals, the plurality of bit lines are arranged along a first direction, and each bit line is S-shaped. The preparation method of the memory comprises the following steps of: providing a substrate; forming a plurality of bit line trenches on the substrate; forming a first isolation layer in each bit line trench; forming bit lines on the first isolation layers; forming a second isolation layer on the bit lines; removing the substrate between adjacent isolation walls, wherein each isolation wall comprises the first isolation layer, the bit lines and the second isolation layer; and forming a third isolation layer in a gap between the adjacent isolation walls, wherein the third isolation layer, the second isolation layer and the first isolation layer jointly form an isolation layer. The memory and the memory prepared by adopting the memory preparation method provided by the embodiment of the invention are high in integration level.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a memory and a preparation method thereof. Background technique [0002] A dynamic random access memory (DRAM for short) is a semiconductor memory capable of writing and reading data at high speed and randomly, and is widely used in data storage devices or devices. [0003] In the existing DRAM, the shallow trench isolation structure is generally formed first to define the active area, and then the buried word lines are formed by etching in the active area, and the bit line contact columns are formed between the buried word lines. Plug, then connect each line to contact the plunger through the bit line; and the more mainstream DRAM in the prior art is 3HPAA by 2HPWL structure, 3HPAA by 2HPWL to determine the area of ​​a bit unit (English full name cell bit), 3HPAA by 2HPWL means 3 times the half pitch of the active area (full English name active region, English abbreviati...

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Problems solved by technology

However, the DRAM integration of this structure is low

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