Gate feature size control method and field effect transistor

Abstract

The embodiment of the invention provides a gate feature size control method and a field effect transistor, which are applied to a self-aligned double-pattern process, and the method comprises the steps: sequentially forming at least two isolation side walls, a sacrificial layer wrapping each isolation side wall, and a low-temperature oxide layer located on the surface of the sacrificial layer on a gate dielectric layer, wherein the isolation side wall is used for defining the feature size of the gate; sequentially performing etching treatment on the low-temperature oxide layer and the sacrificial layer so as to expose a target isolation side wall in the isolation side walls; and thinning the target isolation side wall to obtain a thinned isolation side wall, and etching the gate dielectric layer through the thinned isolation side wall to form the gate.

Description

technical field [0001] The present application relates to the field of semiconductor technology, and relates to but not limited to a method for controlling the feature size of a gate and a field effect transistor. Background technique [0002] In the self-aligned double patterning (Self-Aligned Double Patterning, SADP) formation process of the gate (Gate, G) of the Fin Field-Effect Transistor (Fin Field-Effect Transistor, FINFET), in order to ensure the diversity of devices, it is necessary A critical dimension (Critical Dimension, CD) reduction is performed on a part of the gate formed at the same time. [0003] In the related art, when reducing the critical dimension of the gate, in the wet cleaning process, a cleaning solution such as concentrated sulfuric acid with a higher concentration will be used. However, the concentrated sulfuric acid with a higher concentration will affect the gate pattern used in the SADP process. The isolation spacer is oxidized and corroded, w...

AI Technical Summary

Problems solved by technology

[0003] In the related art, when reducing the critical dimension of the gate, in the wet cleaning process, a cleaning solution such as concentrated sulfuric acid with a higher concentration will be used. However, the concentrated sulfuric acid with a higher concentration will affect the gate pattern used in the SADP process. Oxidation and corrosion of the isolation spacer cause the edge roughness (Line Edge Roughness, LER) of the isolation spacer to increase, thereby affecting the yield of the gate formation process

Images