Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. The method comprises steps that a substrate including memory cell source regions and a connection region between the memory cell source regions is provided; a zeroth polycrystalline silicon layer is obtained; a dielectric layer and a first polycrystalline silicon layer are sequentially formed, photoresist with a photoetching pattern is formed, the photoetching pattern exposes the first polycrystalline silicon layer in the source electrode region and the connecting region of the memory cell, the exposed first polycrystalline silicon layer in the source electrode region and the connecting region of the memory cell is removed through first-time etching, and the exposed dielectric layer of the source electrode region and the connection region of the memory cell iscompletely removed through second etching, and the zeroth polycrystalline silicon layer of the source electrode region of the memory cell exposed by the photoetching pattern is removed through third etching. In the third etching process, by setting the etching selection ratio of the polycrystalline silicon and the silicon dioxide, at least part of the gate oxide layer is reserved in the connecting region after etching, the substrate is protected against etching damage, and the yield and reliability of the device are improved under the condition that the chip integration level is kept unchanged.

Description

Technical field [0001] The present invention relates to the field of semiconductor technology, and more particularly to a semiconductor device and a method of manufacturing a semiconductor device. Background technique [0002] In the Embedded Flash, EMBEDDED Flash, EMBEDDED Flash, ControlGate etch, CG-ET, and simultaneously etching a etching process of zero-layer polysilicon and the first layer of polysilicon in different films. The structure of the layer region is not the same, in the region where the zero-layer polysilicon (poly0) is missing, such as the connection area between the basic storage unit source area (Cell Source), which is etched to the substrate, resulting in substrate damage (DAMAGE) and forming a pit (PITS). The connection area between the storage unit source region is exactly the contact hole leading area of ​​the source region, and the presence of the pit causes the memory cell source area to contact the contact hole, thereby affecting the yield and reliabilit...

AI Technical Summary

Problems solved by technology

The connection area between the source regions of the memory cells is just the contact hole lead-out region of the source regions. The existence of pits leads to poor contact between the source regions of the memory cells and the contact holes, thereby affecting the yield and reliability of the embedded flash memory device circuit. sex

Images