Pipeline SRAM and operation method thereof

Abstract

The invention discloses a pipeline SRAM and an operation method thereof, and belongs to the technical field of special integrated circuit design. The pipeline SRAM comprises a double word line storage unit, a word line control circuit, a clock circuit and a capacitor sharing type copy bit line circuit; by adopting the double word line storage unit, the time sequence problem caused by word line overlapping during continuous read operation of the SRAM is solved, and the read-write operation delay of the SRAM is effectively reduced. And meanwhile, the enabling delay change of a sensitive amplifier is reduced through the capacitor sharing type copy bit line circuit, and the process deviation resistance of the circuit is improved, so that the performance and the energy efficiency of the SRAM are improved. According to the pipeline SRAM, one-time SRAM operation is divided into three steps, so that the problem that the performance of the SRAM is deteriorated under low voltage is solved.

Description

technical field [0001] The invention relates to the technical field of application-specific integrated circuit design, in particular to a pipelined SRAM and a calculation method thereof. Background technique [0002] With the rapid popularization of consumer electronics such as smartphones, the demand for high-performance and low-power system-on-chip (SoC) continues to rise. In order to achieve the two design goals of high performance and low power consumption, the wide Voltage SRAM design has gradually become a research hotspot in the industry. [0003] As an important component module of SoC, wide-voltage Static Random Access Memory (SRAM) has become a research hotspot in the industry. The performance of SRAM is seriously deteriorated at low voltage, which cannot meet the needs of logic circuits. In the prior art, the difficulties in SRAM design under low voltage include: (1) local process deviation causes a sharp increase in SAE delay variation, which deteriorates the r...

AI Technical Summary

Problems solved by technology

The performance of SRAM is severely deteriorated at low voltage and cannot meet the needs of logic circuits

In the prior art, the difficulties in SRAM design under low voltage include: (1) local process deviation causes a sharp increase in SAE delay variation, which deteriorates the read performance of SRAM; (2) the bit line discharge speed is slow, which increases the read delay of SRAM time and read power consumption

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