Package assembly
A technology for packaging components and devices, which is applied in the direction of electrical components, semiconductor devices, electric solid devices, etc., can solve the problems of increasing the density of input/output pads and increasing the difficulty of die packaging
Pending Publication Date: 2021-07-20
TAIWAN SEMICON MFG CO LTD
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- Description
- Claims
- Application Information
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Problems solved by technology
The density of I / O pads increases rapidly over time, which increases the difficulty of die packaging
Method used
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[0016] The following disclosure provides many different embodiments, or examples, for implementing different features of the presented subject matter. Specific examples of components and arrangements are set forth below to simplify the disclosure. Of course, these are examples only and are not intended to be limiting. For example, in the following description, a first feature formed on or over a second feature may include embodiments where the first feature is formed in direct contact with the second feature, and may also include that additional features may An embodiment formed between a first feature and a second feature such that the first feature and the second feature are not in direct contact. In addition, the present invention may repeat reference numerals and / or letters in various instances. This repetition is for brevity and clarity and does not inherently dictate the relationship between the various embodiments and / or configurations discussed.
[0017] In addition...
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In an embodiment, a device includes: a semiconductor device; and a redistribution structure including: a first dielectric layer; a first grounding feature on the first dielectric layer; a second grounding feature on the first dielectric layer; a first pair of transmission lines on the first dielectric layer, the first pair of transmission lines being laterally disposed between the first grounding feature and the second grounding feature, the first pair of transmission lines being electrically coupled to the semiconductor device; a second dielectric layer on the first grounding feature, the second grounding feature, and the first pair of transmission lines; and a third grounding feature extending laterally along and through the second dielectric layer, the third grounding feature being physically and electrically coupled to the first grounding feature and the second grounding feature, wherein the first pair of transmission lines extend continuously along a length of the third grounding feature.
Description
technical field [0001] Embodiments of the present invention relate to packaging assemblies. Background technique [0002] As semiconductor technology continues to evolve, integrated circuit dies are becoming smaller and smaller. In addition, more functions are integrated into the chip. Therefore, the number of input / output (I / O) pads required by the die increases, while the area available for the I / O pads decreases. Over time, the density of I / O pads increases rapidly, which increases the difficulty of die packaging. [0003] In some packaging techniques, the wafer is singulated into integrated circuit dies prior to packaging. An advantageous feature of this packaging technology is that fan-out packaging can be formed, which allows redistribution of input / output pads on the die to a larger area. Therefore, the number of input / output pads on the die surface can be increased. Contents of the invention [0004] In an embodiment, a device includes: a semiconductor device;...
Claims
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IPC IPC(8): H01L23/48
CPCH01L24/02H01L23/48H01L2224/0231H01L2224/02331H01L2224/02379H01L21/6835H01L2221/68345H01L2221/68359H01L23/552H01L25/18H01L21/4857H01L23/49822H01L23/49833H01L23/49816H01L24/24H01L2224/24225H01L23/66H01L23/5383H01L21/4853H01L24/81H01L23/3128H01L24/19H01L2223/6627H01L2221/68381H01L2924/1431H01L2924/1434H01L2224/24137H01L23/5386
Inventor 陈建勋余振华刘重希吴俊毅王守怡
Owner TAIWAN SEMICON MFG CO LTD