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FPGA (Field Programmable Gate Array) chip for privacy calculation, heterogeneous processing system and calculation method

A processing system and chip technology, applied in the field of privacy computing, can solve problems such as time loss, and achieve the effects of relieving the pressure on storage space, improving computing efficiency, and reducing data transmission

Pending Publication Date: 2021-07-27
CLUSTAR TECH LO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] This application provides an FPGA chip for privacy computing, a privacy computing heterogeneous processing system and a computing method to solve the problem of time loss caused by multiple data transmissions between the host computer and the FPGA chip

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  • FPGA (Field Programmable Gate Array) chip for privacy calculation, heterogeneous processing system and calculation method
  • FPGA (Field Programmable Gate Array) chip for privacy calculation, heterogeneous processing system and calculation method
  • FPGA (Field Programmable Gate Array) chip for privacy calculation, heterogeneous processing system and calculation method

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Embodiment Construction

[0060] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

[0061] The flow charts shown in the drawings are just illustrations, and do not necessarily include all contents and operations / steps, nor must they be performed in the order described. For example, some operations / steps can be decomposed, combined or partly combined, so the actual order of execution may be changed according to the actual situation.

[0062] It should be understood that the terms used in the specification of this application are for the purpose of ...

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Abstract

The invention provides an FPGA chip for privacy calculation, a heterogeneous processing system and a calculation method. The FPGA chip comprises a task management module, a calculation module and a memory, wherein the memory is used for storing source data sent by the upper computer; the task management module is used for receiving task information sent by an upper computer, reading the source data from the memory according to the task information and sending the source data to the calculation module; the calculation module is used for calculating the source data to obtain result data; and the task management module is also used for storing the result data to the memory, and reading the result data as partial source data or all source data for next calculation according to the task information of the upper computer. The FPGA chip can support continuous use of result data stored in the chip during next calculation, so that data interaction between the FPGA chip and an upper computer is reduced, time loss is reduced, calculation efficiency is improved, and storage pressure of the upper computer is relieved.

Description

technical field [0001] The present application relates to the field of private computing, and in particular to an FPGA chip for private computing, a heterogeneous processing system for private computing, and a computing method. Background technique [0002] The FPGA chip is a programmable hardware chip with the characteristics of high flexibility, high parallelism and low delay processing. Due to the characteristics of strong computing power and low latency, FPGA chips play an important role in various fields, especially in the field of heterogeneous computing, where FPGA chips can greatly alleviate the computing power bottleneck of algorithms. In the heterogeneous privacy computing heterogeneous processing system, the FPGA chip and the host computer exchange data through a hardware interface such as PCIe, which will cause a certain transmission delay. In application scenarios such as machine learning, the training data often needs to be calculated through multiple iteratio...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F21/60
CPCG06F21/602
Inventor 王玮胡水海
Owner CLUSTAR TECH LO LTD