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Algorithm development method and device

An algorithm and bus technology, applied in the field of algorithm development methods and devices, can solve problems such as not supporting multiple AXI buses

Pending Publication Date: 2021-08-20
BEIJING JINGWEI HIRAIN TECH CO INC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] In view of this, the embodiment of the present invention discloses an algorithm development method and device, which solves the problem in the prior art that code development tools do not support multiple AXI buses, and improves the efficiency of data transmission

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  • Algorithm development method and device

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Embodiment Construction

[0058] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0059] refer to figure 1 , which shows a schematic flowchart of an algorithm development method provided by an embodiment of the present invention. In this embodiment, the method includes:

[0060] S101: Obtain a pre-generated FPGA model;

[0061] In this embodiment, the FPGA model includes multiple algorithm modules, and the FPGA model is used to run on the FPGA after the code is generated.

[0062] Among them, the FPGA model can be built by the user itself...

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Abstract

The invention discloses an algorithm development method and device, and the method comprises the steps: adding at least one AXI bus module after an FPGA model is obtained, and generating a first FPGA code module according to the FPGA model and the AXI bus module connected with the FPGA model; and the first FPGA code module comprises a second FPGA code corresponding to the FPGA model, an AXI bus code corresponding to the AXI bus module and a connection relation between the second FPGA code and the AXI bus code, and in the process of generating the AXI bus codes, different identifiers are adopted to mark AXI signals in different AXI bus codes. Therefore, the AXI signals in the AXI bus codes generated by the AXI bus module are distinguished, and the purpose of data transmission through multiple paths of AXI buses is achieved.

Description

technical field [0001] The invention relates to the field of software, in particular to an algorithm development method and device. Background technique [0002] As far as algorithm development is concerned, at present, technical personnel mainly write codes for the realization of algorithms, or build algorithm models through modules provided by existing tools, for example, build algorithm models through the Simulink environment in MATLAB, and then build Algorithmic models are converted into code. [0003] For the algorithm model, the current code generation tools usually only support single-channel data transmission. To achieve the purpose of multi-channel data transmission, users need to write related programs by themselves, but this method is difficult to implement, or through a data channel , sequentially transmit the output data, the data transmission efficiency of this method is very low. [0004] Therefore, there is an urgent need for a code generation tool to reali...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F8/35G06F8/41G06F13/42
CPCG06F8/35G06F8/451G06F13/4208Y02D10/00
Inventor 罗晓晖郭港张明瀚成一诺
Owner BEIJING JINGWEI HIRAIN TECH CO INC