P-type semi-stacked subthreshold standard cell based on Schmidt trigger circuit
A technology of Schmitt trigger and standard cell, which is applied in the direction of logic circuit with logic function, field effect transistor reliability improvement, reliability improvement modification, etc., can solve the problems of stability and reliability not being improved, and achieve Improve the effect of stability and reliability, high stability and reliability, low leakage current and delay
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Embodiment 1
[0022] Embodiment one: if Figure 1 to Figure 4 As shown, a P-type semi-stacked sub-threshold standard cell based on a Schmitt trigger circuit includes a pull-up network, a pull-down network, a gate feedback PMOS stack module, and a parallel NMOS module group; the pull-up network consists of n PMOS transistors Composed in series, n is an integer greater than or equal to 2, and the source of the first PMOS transistor is connected to the power supply V DD, the drain of the mth PMOS transistor is connected to the source of the m+1th PMOS transistor and its connection terminal is the mth stack node Um of the pull-up network, m=1, 2,..., n-1, the The drain of n PMOS transistors is the output terminal of the pull-up network, the gate of the kth PMOS transistor is the kth input terminal of the pull-up network, k=1, 2,..., n; the pull-down network is connected in parallel by n NMOS transistors Composition, the drains of n NMOS transistors are connected and their connection ends are t...
Embodiment 2
[0025] Embodiment 2: This embodiment is basically the same as Embodiment 1, the only difference is that in this embodiment, the output terminal OUT of the P-type semi-stacked sub-threshold standard cell is connected to an inverter, such as Figure 5 As shown, the inverter includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a first NMOS transistor N1, a second NMOS transistor N2 and a third NMOS transistor N3, and the source of the first PMOS transistor P1 The pole is connected to the power supply, the gate of the first PMOS transistor P1, the gate of the second PMOS transistor P2, the gate of the first NMOS transistor N1 and the gate of the second NMOS transistor N2 are connected, and the connection terminal is the inverter The input terminal, the input terminal of the inverter is connected to the output terminal of the P-type semi-stacked sub-threshold standard cell, the drain of the first PMOS transistor P1, the source of the second P...
Embodiment 3
[0027] Embodiment 3: This embodiment is basically the same as Embodiment 1, the only difference is that in this embodiment, the value of n is 3, the pull-up network is composed of 3 PMOS transistors M7, M8 and M9 connected in series, and the pull-down network is composed of 3 NMOS transistors M10, M11 and M12 are connected in parallel, the gate feedback PMOS stack module is composed of two PMOS transistors M13 and M14, and the parallel NMOS module group is composed of two parallel NMOS modules, of which the first parallel NMOS module is composed of one NMOS transistor M15 The second parallel NMOS module is composed of two NMOS transistors M16 and M17. At this time, the P-type semi-stacked sub-threshold standard unit is a three-input NOR gate. The specific circuit is as follows Figure 8 shown.
[0028] In the three-input NOR gate of this embodiment, PMOS transistors M7, M8 and M9, PMOS transistors M13 and M14, NMOS transistors M15, NMOS transistors M16 and M17 are composed of ...
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